吉林师范大学学报：自然科学版
吉林師範大學學報：自然科學版
길림사범대학학보：자연과학판
Jilin Normal University Journal:Natural Science Edition
2012年
2期
119-120,124
,共3页
脉冲信号%可变周期%占空比%FPGA
脈遲信號%可變週期%佔空比%FPGA
맥충신호%가변주기%점공비%FPGA
pulse signal%variable cycles%duty cycle%FPGA
数字信号由于具有抗干扰能力强、无噪声积累,便于存储、处理和交换等一系列优点,已经成为现代控制领域的主要处理信号.要求改变脉冲信号的周期、占空比和输出脉冲个数可控的电路模块在很多控制领域都有应用.本文介绍了一种基于FPGA芯片的可控输出信号周期、占空比和信号个数的设计方法.应用时钟管理模块对输入时钟进行倍频来提高输出信号的周期范围和精度;调用IP核来完成相应的数学运算;应用两个可控减计数器来控制每一周期内高低电平的持续时间;应用数量控制计数器对输出的脉冲进行计数,控制输出量.该设计运行在ALTERA公司的clcyone芯片上,取得良好的效果,具有灵活高效的优点.
數字信號由于具有抗榦擾能力彊、無譟聲積纍,便于存儲、處理和交換等一繫列優點,已經成為現代控製領域的主要處理信號.要求改變脈遲信號的週期、佔空比和輸齣脈遲箇數可控的電路模塊在很多控製領域都有應用.本文介紹瞭一種基于FPGA芯片的可控輸齣信號週期、佔空比和信號箇數的設計方法.應用時鐘管理模塊對輸入時鐘進行倍頻來提高輸齣信號的週期範圍和精度;調用IP覈來完成相應的數學運算;應用兩箇可控減計數器來控製每一週期內高低電平的持續時間;應用數量控製計數器對輸齣的脈遲進行計數,控製輸齣量.該設計運行在ALTERA公司的clcyone芯片上,取得良好的效果,具有靈活高效的優點.
수자신호유우구유항간우능력강、무조성적루,편우존저、처리화교환등일계렬우점,이경성위현대공제영역적주요처리신호.요구개변맥충신호적주기、점공비화수출맥충개수가공적전로모괴재흔다공제영역도유응용.본문개소료일충기우FPGA심편적가공수출신호주기、점공비화신호개수적설계방법.응용시종관리모괴대수입시종진행배빈래제고수출신호적주기범위화정도;조용IP핵래완성상응적수학운산;응용량개가공감계수기래공제매일주기내고저전평적지속시간;응용수량공제계수기대수출적맥충진행계수,공제수출량.해설계운행재ALTERA공사적clcyone심편상,취득량호적효과,구유령활고효적우점.
Digital signal has been the chief processing signal in the field of modern controlling because it has a series of advantages such as strong anti-interference,noise-free accumulation and easy to store,process and exchange.There are many applications in requirements to change the cycle of the pulse signal,duty cycle and the module of output pulse controlled.This paper discusses a method to finish these works based on the FPGA.We increase the cycle of the output signal range and accuracy by using clock management module;call IP core to complete the appropriate math problems;control the duration of each cycle of high and low by using two controllable down counter;counter the output and control the output.The design achieves a good result on the chip made of ALTERA company and it has the feature of flexibility.
