CAJ | 학술논문

文章介绍了星载遥感CCD相机高性能时序发生器的研制过程。根据TDICCD驱动时序信号的特点，采用先进的EDA工具（包括Libero IDE、Synplify Pro、Modersim等）对时序发生器进行了设计、综合、仿真。研究了反熔丝现场门阵列（Field Programmable Gate Aarray，FPGA）器件自身结构的特点，在自动布局布线的基础上采用人工干预的方法对局部寄存器和逻辑门进行了合理布局布线，优化输出I/O时序，使得驱动CCD的水平转移信号之间偏斜最小，并精确调整了水平转移信号的相位关系，从而提高了CCD模拟信号的精度，使时序发生器达到最佳性能，同时缩短了研制周期、降低了成本。
문장개소료성재요감CCD상궤고성능시서발생기적연제과정。근거TDICCD구동시서신호적특점，채용선진적EDA공구（포괄Libero IDE、Synplify Pro、Modersim등）대시서발생기진행료설계、종합、방진。연구료반용사현장문진렬（Field Programmable Gate Aarray，FPGA）기건자신결구적특점，재자동포국포선적기출상채용인공간예적방법대국부기존기화라집문진행료합리포국포선，우화수출I/O시서，사득구동CCD적수평전이신호지간편사최소，병정학조정료수평전이신호적상위관계，종이제고료CCD모의신호적정도，사시서발생기체도최가성능，동시축단료연제주기、강저료성본。
This paper describes how to develop a high-performance timing generator for remote sensing CCD camera on satellite. According to the characteristics of TDICCD driving timing, the advanced EDA tools, which contain Libero IDE, Synplify Pro, Modelsim and so on, are used to design, synthesize and simulate the high-performance timing generator. By analyzing and studying the characteristics of anti-fuse FPGA chip, part of registers and logic cells are placed manually based on automatic layout&routing, which can make the driv-ing signals’ Clock-to-output delay time skew shorter and adjust the phase relationship accurately, and then the precision of analog signals is improved. Finally, a high-performance timing generator with shorter time and lower cost is achieved.