电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2012年
20期
164-167,170
,共5页
李卫兵%李道通%胡波%王彩凤
李衛兵%李道通%鬍波%王綵鳳
리위병%리도통%호파%왕채봉
FPGA%IP%Core%等精度测频%LCD%VHD
FPGA%IP%Core%等精度測頻%LCD%VHD
FPGA%IP%Core%등정도측빈%LCD%VHD
FPGA%IP Core%equal precision frequency%LCD%Verilog HDL
基于Altera公司FPGA芯片EP2C8Q208,嵌入MC8051 IP Core,用C语言对MC8051 IP Core进行编程,以其作为控制核心,实现系统控制。在FPGA芯片中,利用Verilog HDL语言进行编程,设计了以MC8051 IP Core为核心的控制模块、计数模块、锁存模块和LCD显示模块等几部分,实现了频率的自动测量,测量范围为0.1Hz~50MHz,测量误差0.01%。并实现测频率、周期、占空比等功能。
基于Altera公司FPGA芯片EP2C8Q208,嵌入MC8051 IP Core,用C語言對MC8051 IP Core進行編程,以其作為控製覈心,實現繫統控製。在FPGA芯片中,利用Verilog HDL語言進行編程,設計瞭以MC8051 IP Core為覈心的控製模塊、計數模塊、鎖存模塊和LCD顯示模塊等幾部分,實現瞭頻率的自動測量,測量範圍為0.1Hz~50MHz,測量誤差0.01%。併實現測頻率、週期、佔空比等功能。
기우Altera공사FPGA심편EP2C8Q208,감입MC8051 IP Core,용C어언대MC8051 IP Core진행편정,이기작위공제핵심,실현계통공제。재FPGA심편중,이용Verilog HDL어언진행편정,설계료이MC8051 IP Core위핵심적공제모괴、계수모괴、쇄존모괴화LCD현시모괴등궤부분,실현료빈솔적자동측량,측량범위위0.1Hz~50MHz,측량오차0.01%。병실현측빈솔、주기、점공비등공능。
This design is based on Altera's cyclone II series FPGA,and used Verilog HDL hardware description language as a tool for the design of digital frequency meter.with its core as a system control,the MC8051 IP Core embedded in FPGA chip,using C language programm on the MC8051 IP Core;in the FPGA chip using Verilog HDL programming language designed the MC8051 IP Core,counting modules,latching module and LCD display modules and other parts and realized the automatic measurement of frequency,namely: adaptive regulation,measurement range 0.1 Hz to 50 MHz,measurement error is small.Enables measurement frequency,period,duty cycle and other functions.
