CAJ | 학술논문

指令集模拟器（ISS）是研究新处理器架构必不可少的方法,研究基于AltiVec指令集建立SystemC模型,提出利用底层虚拟机技术来实现AltiVec ISS.实验表明,该模式比目前实现ISS的几种方法,如解释型编译、静态型编译、动态翻译技术等性能更为优化,且具有一定的灵活性.
지령집모의기（ISS）시연구신처리기가구필불가소적방법,연구기우AltiVec지령집건립SystemC모형,제출이용저층허의궤기술래실현AltiVec ISS.실험표명,해모식비목전실현ISS적궤충방법,여해석형편역、정태형편역、동태번역기술등성능경위우화,차구유일정적령활성.
Instruction set simulator（ISS） are indispensable methods for studying new processor architecture.This paper present an approach to design AltiVec instruction set simulation model based on SystemC where we have developed and integrated the low level virtual machine optimization technique.For four simulation varieties of the same instruction set,we made an experiment to compare their performance.The result shows that the performance and flexibility of AltiVec instruction set simulator has been optimized by the low level virtual machine optimization technique.