电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2012年
16期
161-163
,共3页
高斯噪声源电路%查表法%非均匀划分%寻址电路
高斯譟聲源電路%查錶法%非均勻劃分%尋阯電路
고사조성원전로%사표법%비균균화분%심지전로
Gaussian noise source circuit%look-up table method%nonuniform partition%addressing circuit
为了实现占用资源少、精度高的高斯噪声源电路。设计了一种新的高斯噪声产生方案，该方案在FPGA上通过线性反馈移位寄存器产生高速均匀分布伪随机数，接着利用均匀分布与高斯分布之间的映射关系生成高斯噪声，并创新地采用非均匀划分的折线逼近映射曲线，同时设计寻址电路，从而减少噪声源占用的资源，改善噪声精度。在XILINX Virtex5 XC5VLX50T上的实现结果表明。该方案仅使用了2％的可配置SLICE和l块片上BRAM，实现了±4σ（盯为标准偏差）的高斯噪声源。时序分析表明其最高频率可达131MHz。
為瞭實現佔用資源少、精度高的高斯譟聲源電路。設計瞭一種新的高斯譟聲產生方案，該方案在FPGA上通過線性反饋移位寄存器產生高速均勻分佈偽隨機數，接著利用均勻分佈與高斯分佈之間的映射關繫生成高斯譟聲，併創新地採用非均勻劃分的摺線逼近映射麯線，同時設計尋阯電路，從而減少譟聲源佔用的資源，改善譟聲精度。在XILINX Virtex5 XC5VLX50T上的實現結果錶明。該方案僅使用瞭2％的可配置SLICE和l塊片上BRAM，實現瞭±4σ（盯為標準偏差）的高斯譟聲源。時序分析錶明其最高頻率可達131MHz。
위료실현점용자원소、정도고적고사조성원전로。설계료일충신적고사조성산생방안，해방안재FPGA상통과선성반궤이위기존기산생고속균균분포위수궤수，접착이용균균분포여고사분포지간적영사관계생성고사조성，병창신지채용비균균화분적절선핍근영사곡선，동시설계심지전로，종이감소조성원점용적자원，개선조성정도。재XILINX Virtex5 XC5VLX50T상적실현결과표명。해방안부사용료2％적가배치SLICE화l괴편상BRAM，실현료±4σ（정위표준편차）적고사조성원。시서분석표명기최고빈솔가체131MHz。
In order to achieve a Gauss noise source circuit with low resource occupation and high precision, a new method is proposed in this paper. The method generate high speed uniformly distributed pseudo-random number by linear feedback shift register on FPGA, Gauss noise is generated according to the mapping relationship between uniform distribution and Gaussian distribution then. Nonuniform partition lines are used to approximate the mapping curve and the corresponding addressing circuit is designed which reduce the occupied resources and improve precision of noise. The implemented design on a XILINX Virtex5 XC5VLX50T utilizes only 2% configurable SLICE and 1 on-chip BRAM to generate Gaussian samples within up to ±4σ, where cr is the standard deviation. Timing analysis shows that the frequency of the circuit can be up to 131 MHz.
