CAJ | 학술논문

针对数字视频图像采集及其显示系统中高速实时的数据需要缓存的问题，提出一种基于FPGA的SDRAM控制器设计。在研究SDRAM的逻辑结构的基础上，利用Verilog语言实现了SDRAM的初始化以及读写操作，同时提出一种仅使用一块SDRAM进行数据写入和读出的乒乓操作的方法，并且使用FIFO实现了异步时钟数据的交换。实验仿真波形图表明该设计能很好的实现SDRAM控制器的数据缓存以及数据读写的乒乓操作。
침대수자시빈도상채집급기현시계통중고속실시적수거수요완존적문제，제출일충기우FPGA적SDRAM공제기설계。재연구SDRAM적라집결구적기출상，이용Verilog어언실현료SDRAM적초시화이급독사조작，동시제출일충부사용일괴SDRAM진행수거사입화독출적핑퐁조작적방법，병차사용FIFO실현료이보시종수거적교환。실험방진파형도표명해설계능흔호적실현SDRAM공제기적수거완존이급수거독사적핑퐁조작。
For the problem of real-time and high-speed data cache in digital video image acquisition and display sys-tem, a design of SDRAM controller based on FPGA is put forward in this paper.On the basis of the logical structure of SDRAM, the SDRAM initialization and operations of reading and writing are achieved by using the Verilog lan-guage, and then a kind of operation data writing and reading using only a SDRAM ping-pong is put forward, at the same time,the data exchange of the asynchronous clock is achieved by using the FIFO.Simulation waveform of experi-mental results show that this design can achieve very good the data cache of SDRAM controller and the ping-pong op-eration of data reading and writing.