CAJ | 학술논문

抗混叠滤波和模数转换器性能严重影响到后续接收机的数字处理。高分辨率A/D转换虽然可改善信号/量化噪声比,但也要求抗混叠滤波器有更低阻带衰减,致使其实现复杂、成本增加。在Tetra系统基带设计中,采用过采样ΣΔ调制可平衡高比特A/D转换与简单抗混叠滤波两者矛盾的要求。在分析ΣΔ调制的噪声整形基础上,针对Tetra系统要求,完成过采样3阶ΣΔ调制器及1/16降速抽取滤波器设计,MATLAB仿真验证了设计的正确和有效性,给出了相关的设计结果。
항혼첩려파화모수전환기성능엄중영향도후속접수궤적수자처리。고분변솔A/D전환수연가개선신호/양화조성비,단야요구항혼첩려파기유경저조대쇠감,치사기실현복잡、성본증가。재Tetra계통기대설계중,채용과채양ΣΔ조제가평형고비특A/D전환여간단항혼첩려파량자모순적요구。재분석ΣΔ조제적조성정형기출상,침대Tetra계통요구,완성과채양3계ΣΔ조제기급1/16강속추취려파기설계,MATLAB방진험증료설계적정학화유효성,급출료상관적설계결과。
The performance of anti-aliasing filters and analog-to-digital converters severely impacts on follow-up digital signal processing. It is known that the higher ratio of signal-to-quantization noise can be achieved with more bits of an A/D converter,but the lower stop-band attenuation for the anti-aliasing filter is also required. In this paper, an oversampling ∑A modulator is used in a baseband receiver design of Tetra system for providing a tradeoff solution. The mechanisms of quantization noise shaping and removal of a ∑A modulator are analyzed. A three-order ∑A modulator and a low-pass filter with 1/16 decimation are designed,and MATLAB-based simulation is carried out for the design verification and relevant results are demonstrated.