CAJ | 학술논문

混合电压I／O接口的静电放电（electrostaticdischarge，ESD）保护设计是小线宽工艺中片上系统（SoC）设计的主要挑战之一。混合电压I／O接口的片上ESD保护既要避免栅氧可靠性问题，又要防止不期望的泄漏电流路径产生。这篇论文讨论了基于堆叠NMOS（Stacked—NMOS，STNMOS）的混合电压I／O接口的ESD保护设计构思和电路实现，通过不同ESD保护设计方案的比较，提出了一个最有效的保护方案。
혼합전압I／O접구적정전방전（electrostaticdischarge，ESD）보호설계시소선관공예중편상계통（SoC）설계적주요도전지일。혼합전압I／O접구적편상ESD보호기요피면책양가고성문제，우요방지불기망적설루전류로경산생。저편논문토론료기우퇴첩NMOS（Stacked—NMOS，STNMOS）적혼합전압I／O접구적ESD보호설계구사화전로실현，통과불동ESD보호설계방안적비교，제출료일개최유효적보호방안。
Electrostatic discharge （ ESD ） protection design for mixed-voltage I/O interfaces has been one of the main challenges of system-on-a-chip （ SoC ） design in minor-line-width processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should prevent the gate-oxide reliability issues and the undesired leakage current paths. The design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces based on STNMOS is discussed in this paper. With comparisons among various ESD protection designs for mixed-voltage I/O circuits, an active ESD protection design of interface circuit is proposed.