单片机与嵌入式系统应用
單片機與嵌入式繫統應用
단편궤여감입식계통응용
MICROCONTROLLER & EMBEDDED SYSTEM
2012年
7期
37-40
,共4页
CAN总线%SOPC%IP核%FPGA
CAN總線%SOPC%IP覈%FPGA
CAN총선%SOPC%IP핵%FPGA
CAN bus%SOPC%IP core%FPGA
分析了CAN总线控制器的工作原理，以SJA1000为模型，提出基于SOPC技术的CAN总线控制器的设计方案，并完成SJA1000IP核的设计；完成了在Altera的CycloneIII型FPGA芯片上集成微处理器核、SJA1000IP核、数据RAM、程序ROM为一体的完整CAN总线通信系统的设计。实验结果验证了SJA1000IP核设计方案的合理性。
分析瞭CAN總線控製器的工作原理，以SJA1000為模型，提齣基于SOPC技術的CAN總線控製器的設計方案，併完成SJA1000IP覈的設計；完成瞭在Altera的CycloneIII型FPGA芯片上集成微處理器覈、SJA1000IP覈、數據RAM、程序ROM為一體的完整CAN總線通信繫統的設計。實驗結果驗證瞭SJA1000IP覈設計方案的閤理性。
분석료CAN총선공제기적공작원리，이SJA1000위모형，제출기우SOPC기술적CAN총선공제기적설계방안，병완성SJA1000IP핵적설계；완성료재Altera적CycloneIII형FPGA심편상집성미처리기핵、SJA1000IP핵、수거RAM、정서ROM위일체적완정CAN총선통신계통적설계。실험결과험증료SJA1000IP핵설계방안적합이성。
The working principle of CAN bus controller is analyzed. Taking SJA1000 as model, a design of CAN bus controller is pro- posed based on SOPC technology, and the design of SJA1000 IP core is achieved. A integral CAN bus communication system is realized on Altera Cyclone III FPGA chip,which integrates microprocessor core, SJA1000 IP core, data RAM and program ROM. Experimental result verifies the rationality of SJA1000 IP core design.
