电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2012年
14期
120-122
,共3页
三维小波变换%VLSI%提升算法%verilog模型
三維小波變換%VLSI%提升算法%verilog模型
삼유소파변환%VLSI%제승산법%verilog모형
3D DWT%VLSI%lifting scheme%model of verilog
文中通过深入研究三维离散小波变换（3D DWT）核心算法并根据序列图像编码的特点,设计并实现了一种适合硬件实现的高效的三维小波变换VLSI结构。编写了相应verilog模型,并进行了仿真和逻辑综合。仿真结果表明行列滤波并行处理并采用流水线设计方法,加快了运算速度,有效降低了片内存储容量。
文中通過深入研究三維離散小波變換（3D DWT）覈心算法併根據序列圖像編碼的特點,設計併實現瞭一種適閤硬件實現的高效的三維小波變換VLSI結構。編寫瞭相應verilog模型,併進行瞭倣真和邏輯綜閤。倣真結果錶明行列濾波併行處理併採用流水線設計方法,加快瞭運算速度,有效降低瞭片內存儲容量。
문중통과심입연구삼유리산소파변환（3D DWT）핵심산법병근거서렬도상편마적특점,설계병실현료일충괄합경건실현적고효적삼유소파변환VLSI결구。편사료상응verilog모형,병진행료방진화라집종합。방진결과표명행렬려파병행처리병채용류수선설계방법,가쾌료운산속도,유효강저료편내존저용량。
A VLSI architecture with highly efficient for three dimensional discrete wavelet transform（3D DWT） is presented by studying 3D DWT core algorithm in deepness and according to image characteristic.The hardware structure of 3D wavelet video coder is designed,and the verilog modules are programmed,simulated and synthesized.The result show that processing a few datum with row filter operations that are paralleling with column filter operations,the on-chip memory capacity is progressively reduced.Furthermore,the architecture of the row filter and column filter and a pipelined method adopt that can speed up the transforms and improves the hardware utilization.
