CAJ | 학술논문

介绍了一种用于流水线模数转换器前端的低电压、低功耗、高速采样/保持电路。该电路基于电容翻转型结构,采用全差分折叠共源共栅两级运放,能实现高增益、大单位增益带宽和大摆幅。在SMIC 0.13μm工艺、1.2V电压下仿真,其性能满足10bit精度、120MHz采样频率的ADC的要求,整个电路功耗约15mW。
개소료일충용우류수선모수전환기전단적저전압、저공모、고속채양/보지전로。해전로기우전용번전형결구,채용전차분절첩공원공책량급운방,능실현고증익、대단위증익대관화대파폭。재SMIC 0.13μm공예、1.2V전압하방진,기성능만족10bit정도、120MHz채양빈솔적ADC적요구,정개전로공모약15mW。
We present the design of a high-speed,low voltage and low power sample-and-hold circuit(S/H)for pipelined analog digital converter(ADCs) at the front end.This circuit is based on capacitor flip-around architecture with fully differential folded cascade two-stage operational transconductance amplifier(OTA),which has the advantage of the high DC gain,large unity gain bandwidth and large swing.The entire S/H circuit is designed in SMIC 1.2V 0.13μm CMOS technology and the 10bit resolution at 120MHz sampling rate is achieved.The total power dissipation is about 15mW.