CAJ | 학술논문

针对《数字逻辑》课程实验的特点，提出运用MatLab软件进行数字逻辑实验设计和仿真的方法，通过创建加／减法器、同步十进制计数器的电路模型，在MatLab／Simulink环境下对实验电路进行仿真，仿真结果验证该实验方法的正确性和可行性。
침대《수자라집》과정실험적특점，제출운용MatLab연건진행수자라집실험설계화방진적방법，통과창건가／감법기、동보십진제계수기적전로모형，재MatLab／Simulink배경하대실험전로진행방진，방진결과험증해실험방법적정학성화가행성。
Aiming at the characteristic of Digital Logic experiment, puts forward a method of digital logic experiment design and simulation using the MatLab software. By creating circuit models of the adder/subtracter and the synchronous decimal counter, makes the simulation experiment in MatLab/Simulink. Simulation result verifies that this experimental method is correct and feasible.