无线互联科技
無線互聯科技
무선호련과기
WUXIAN HULIAN KEJI
2013年
11期
132-134
,共3页
SPI协议%IP核%Verilog HDL%FPGA
SPI協議%IP覈%Verilog HDL%FPGA
SPI협의%IP핵%Verilog HDL%FPGA
SPI protocol%IP core%Verilog HDL%FPGA
基于APB总线接口，设计了一种可灵活配置为Master/Slave模式、设置传输速率、支持DMA功能并适用于4种时钟模式的SPI 协议IP核。首先介绍了SPI协议标准，然后详细说明了该IP核的系统结构、接口信号和子模块设计，并使用了Verilog HDL语言实现硬件设计。最后通过了FPGA时序仿真，验证了该设计的正确性。该IP核已成功用于一款通信芯片，证明了该IP核在实际工程中的可行性。
基于APB總線接口，設計瞭一種可靈活配置為Master/Slave模式、設置傳輸速率、支持DMA功能併適用于4種時鐘模式的SPI 協議IP覈。首先介紹瞭SPI協議標準，然後詳細說明瞭該IP覈的繫統結構、接口信號和子模塊設計，併使用瞭Verilog HDL語言實現硬件設計。最後通過瞭FPGA時序倣真，驗證瞭該設計的正確性。該IP覈已成功用于一款通信芯片，證明瞭該IP覈在實際工程中的可行性。
기우APB총선접구，설계료일충가령활배치위Master/Slave모식、설치전수속솔、지지DMA공능병괄용우4충시종모식적SPI 협의IP핵。수선개소료SPI협의표준，연후상세설명료해IP핵적계통결구、접구신호화자모괴설계，병사용료Verilog HDL어언실현경건설계。최후통과료FPGA시서방진，험증료해설계적정학성。해IP핵이성공용우일관통신심편，증명료해IP핵재실제공정중적가행성。
Based on APB Bus, we designed an IP Core of SPI protocol, which could be configured as SPI Master or SPI Slave ,could set different transmission speed, could support DMA function, and could work in any one of the four clock modes. First,The paper introduces the standard of SPI protocol.Then,it describes the structure of the IP Core based on Verilog HDL. The module has already been verified by FPGA platform. Presently, the SPI IP Core had been applied in a chip to show the validity of this design in engineering application.
