时间频率学报
時間頻率學報
시간빈솔학보
JOURNAL OF TIME AND FREQUENCY
2012年
2期
88-95
,共8页
低频时码%数字接收机%数字滤波%现场可编程门阵列(FPGA)
低頻時碼%數字接收機%數字濾波%現場可編程門陣列(FPGA)
저빈시마%수자접수궤%수자려파%현장가편정문진렬(FPGA)
low frequency time-code%digital receiver%digital filter%field programmable gate array(FPGA)
介绍了一种基于FPGA的便携式低频时码接收机系统的设计方案。该接收机的特点是体积小,功耗低,方便户外工作人员携带。描述了该接收机的硬件系统结构,给出了软件算法。硬件结构中,使用了ALTERA公司的EP2C70F672C8芯片,软件部分在QuartusⅡ开发环境下完成。系统测试结果表明,按本方案设计的接收机集成度高,可靠性好,易扩展,易升级,具有一定的实用价值。
介紹瞭一種基于FPGA的便攜式低頻時碼接收機繫統的設計方案。該接收機的特點是體積小,功耗低,方便戶外工作人員攜帶。描述瞭該接收機的硬件繫統結構,給齣瞭軟件算法。硬件結構中,使用瞭ALTERA公司的EP2C70F672C8芯片,軟件部分在QuartusⅡ開髮環境下完成。繫統測試結果錶明,按本方案設計的接收機集成度高,可靠性好,易擴展,易升級,具有一定的實用價值。
개소료일충기우FPGA적편휴식저빈시마접수궤계통적설계방안。해접수궤적특점시체적소,공모저,방편호외공작인원휴대。묘술료해접수궤적경건계통결구,급출료연건산법。경건결구중,사용료ALTERA공사적EP2C70F672C8심편,연건부분재QuartusⅡ개발배경하완성。계통측시결과표명,안본방안설계적접수궤집성도고,가고성호,역확전,역승급,구유일정적실용개치。
A design of portable low frequency time-code receiver based on FPGA（field programmable gate array） is introduced.The receiver is characterized by small volume and low power consumption,and it is very convenient to carry it outdoors.The design of hardware structure and software algorithm is described in this paper.The chip of EP2C70F672C8 produced by the ALTERA company is adopted in the hardware structure,and the software design is completed in Quartus Ⅱ environment.The experimental results indicate that this receiver has merits such as high integrity level,good reliability,and being easy to be expanded and upgraded.Thus this receiver is of certain practical value.
