CAJ | 학술논문

为了适应三维图形分块渲染的需要,使得像素经过渲染后能够快速的输出,文中给出了一种分块的光栅操作结构,各个块并行工作。每个并行模块均能实现渲染后片段的测试、混合、逻辑操作和屏蔽处理。该设计结构能够在一个时钟周期输出4个像素。设计进行了基于ModelSim的功能仿真并在Xilinx的FPGA上进行了综合实现,结果表明设计可行。
위료괄응삼유도형분괴선염적수요,사득상소경과선염후능구쾌속적수출,문중급출료일충분괴적광책조작결구,각개괴병행공작。매개병행모괴균능실현선염후편단적측시、혼합、라집조작화병폐처리。해설계결구능구재일개시종주기수출4개상소。설계진행료기우ModelSim적공능방진병재Xilinx적FPGA상진행료종합실현,결과표명설계가행。
To meet the demand for tiled rendering 3D graphics, and to quickly output the ren- dered pixels, it proposed the architecture of tiled raster logic operation. The tile processors operate in parallel. Each processor implements fragment test, blending, logic operations and mask operations. The implementation is able to output four pixels each clock period. The design is simulated on ModelSim and implemented on Xilinx FPGA. The result shows that the design is workable.