电子科技
電子科技
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IT AGE
2012年
9期
88-90,114
,共4页
李帅人%周晓明%吴家国
李帥人%週曉明%吳傢國
리수인%주효명%오가국
带隙基准%温度系数%电源电压抑制比%高阶补偿
帶隙基準%溫度繫數%電源電壓抑製比%高階補償
대극기준%온도계수%전원전압억제비%고계보상
bandgap reference%temperature coefficient%power supply voltage rejection ratio%high order com- pensation
基于TSMC40nmCMOS工艺设计了一种高精度带隙基准电路。采用Spectre工具仿真,结果表明,带隙基准输出电压在温度为-40—125℃的范围内具有10×10^-6/℃的温度系数,在电源电压在1.5-5.5V变化时,基准输出电压随电源电压变化仅为0.42mV,变化率为0.23mv/V,采用共源共栅电流镜后,带隙基准在低频下的电源电压抑制比为-72dB。
基于TSMC40nmCMOS工藝設計瞭一種高精度帶隙基準電路。採用Spectre工具倣真,結果錶明,帶隙基準輸齣電壓在溫度為-40—125℃的範圍內具有10×10^-6/℃的溫度繫數,在電源電壓在1.5-5.5V變化時,基準輸齣電壓隨電源電壓變化僅為0.42mV,變化率為0.23mv/V,採用共源共柵電流鏡後,帶隙基準在低頻下的電源電壓抑製比為-72dB。
기우TSMC40nmCMOS공예설계료일충고정도대극기준전로。채용Spectre공구방진,결과표명,대극기준수출전압재온도위-40—125℃적범위내구유10×10^-6/℃적온도계수,재전원전압재1.5-5.5V변화시,기준수출전압수전원전압변화부위0.42mV,변화솔위0.23mv/V,채용공원공책전류경후,대극기준재저빈하적전원전압억제비위-72dB。
A High Precision CMOS voltage reference circuit is designed by the TSMC 40 nm CMOS process. Spectre simulation shows that the temperature coefficient is 10×10^-6/℃ in the temperature range from -40 to 125. The change of the voltage reference is 0. 42 mV, and the ehange rate is 0. 23 mV/V in the power supply voltage range of 1.5 -3.3 V. PSRR is 72 dB after using the cascode current mirror.