电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2012年
7期
139-143,147
,共6页
集成电路%同步电路%图像传感器%时钟同步
集成電路%同步電路%圖像傳感器%時鐘同步
집성전로%동보전로%도상전감기%시종동보
integrated circuit%synchronizer%image sensor%clock synchronization
为使跨时钟域信号能够被目标时钟正确采集,提出并总结了几种同步方法,详尽论述了这些方法所涉及的存储器计算和synthesis设置。跨时钟域信号的同步方法应根据源时钟与目标时钟的相位关系、该信号的时间宽度和多个跨时钟域信号之间的时序关系来选择。如果两时钟有确定的相位关系,可由目标时钟直接采集跨时钟域信号,且在synthesis中应设此两时钟为同步关系;否则,需要借助FIFO(First in,First out),在synthesis时,此两时钟必须设为false path关系。跨时钟域信号的宽度至少应为目标时钟周期的两倍。对于彼此有确定时序关系的多个跨时钟域信号,在同步前应使其保持足够距离。所述方法在CMOS(Complementary Metal Oxide Semiconductor)图像传感器的设计中被实际应用。经仿真和芯片的系统验证,该图像传感器可以正确完成信号在各时钟间的同步,并以60帧/s的速率正确输出分辨率为1 280×720的数据。
為使跨時鐘域信號能夠被目標時鐘正確採集,提齣併總結瞭幾種同步方法,詳儘論述瞭這些方法所涉及的存儲器計算和synthesis設置。跨時鐘域信號的同步方法應根據源時鐘與目標時鐘的相位關繫、該信號的時間寬度和多箇跨時鐘域信號之間的時序關繫來選擇。如果兩時鐘有確定的相位關繫,可由目標時鐘直接採集跨時鐘域信號,且在synthesis中應設此兩時鐘為同步關繫;否則,需要藉助FIFO(First in,First out),在synthesis時,此兩時鐘必鬚設為false path關繫。跨時鐘域信號的寬度至少應為目標時鐘週期的兩倍。對于彼此有確定時序關繫的多箇跨時鐘域信號,在同步前應使其保持足夠距離。所述方法在CMOS(Complementary Metal Oxide Semiconductor)圖像傳感器的設計中被實際應用。經倣真和芯片的繫統驗證,該圖像傳感器可以正確完成信號在各時鐘間的同步,併以60幀/s的速率正確輸齣分辨率為1 280×720的數據。
위사과시종역신호능구피목표시종정학채집,제출병총결료궤충동보방법,상진논술료저사방법소섭급적존저기계산화synthesis설치。과시종역신호적동보방법응근거원시종여목표시종적상위관계、해신호적시간관도화다개과시종역신호지간적시서관계래선택。여과량시종유학정적상위관계,가유목표시종직접채집과시종역신호,차재synthesis중응설차량시종위동보관계;부칙,수요차조FIFO(First in,First out),재synthesis시,차량시종필수설위false path관계。과시종역신호적관도지소응위목표시종주기적량배。대우피차유학정시서관계적다개과시종역신호,재동보전응사기보지족구거리。소술방법재CMOS(Complementary Metal Oxide Semiconductor)도상전감기적설계중피실제응용。경방진화심편적계통험증,해도상전감기가이정학완성신호재각시종간적동보,병이60정/s적속솔정학수출분변솔위1 280×720적수거。
To have destination clock sample correctly signals across clock domains,this paper proposes the several synchronous methods and discusses how to calculate depth of corresponding memory and how to set the synthesis parameters.According to phase relation between source and destination clocks,width of signals and timing relation between the signals,the synchronous methods are chosen.If the phase relation is certain,destination clock may directly sample signals across clock domains,and synchronous relation is set to the clocks in synthesis.Otherwise,FIFO(First in,First out) must be applied,and paths across the clock domains must be set to false path in synthesis.Width of signals is at least twice as long as period of destination clock.If signals have certain order relation with each other,sufficient distance must be held in source clock domain.The methods were applied in a practical design for CMOS(Complementary Metal Oxide Semiconductor) image sensor.By simulation and chip system verification,the sensor can synchronize signals between clock domains and transmit correctly images of resource 1 280×720 at 60 fps.