电力系统保护与控制
電力繫統保護與控製
전력계통보호여공제
POWER SYSTM PROTECTION AND CONTROL
2013年
17期
116-121
,共6页
董新生%段太钢%周芝萍%伍旭刚%吴双惠%张乔宾
董新生%段太鋼%週芝萍%伍旭剛%吳雙惠%張喬賓
동신생%단태강%주지평%오욱강%오쌍혜%장교빈
合并单元%数据同步%采样精确度%Xenomai%实时Linux%FPGA
閤併單元%數據同步%採樣精確度%Xenomai%實時Linux%FPGA
합병단원%수거동보%채양정학도%Xenomai%실시Linux%FPGA
merging unit%data synchronization%sampling precision%Xenomai%real-time Linux%FPGA
同步采样测试包含了数据同步测试与采样值精确度测试两个方面,是合并单元最重要的指标之一。在分析了合并单元同步采样测试的现状与存在的技术难点的基础上,介绍了一种基于实时Linux系统结合FPGA实时子系统、接口信号可扩展的合并单元同步采样测试装置的具体实现方法。该方法将FPGA的普通I/O管脚构成一个信号接口总线,通过读取信号接口板的I2C总线EEPROM保存的信息,来分配FPGA管脚的功能,从而实现接口信号的可扩展性,满足合并单元输入输出信号灵活多变的需求。同时,FPGA实现了采样值报文的接收,记录报文接收时标,采样值报文的生成与发送以及模拟MII接口直接与PHY通信等功能。结果表明,本测试装置能准确反映合并单元的数据同步精度、采样值精度,具有较强的实用价值。
同步採樣測試包含瞭數據同步測試與採樣值精確度測試兩箇方麵,是閤併單元最重要的指標之一。在分析瞭閤併單元同步採樣測試的現狀與存在的技術難點的基礎上,介紹瞭一種基于實時Linux繫統結閤FPGA實時子繫統、接口信號可擴展的閤併單元同步採樣測試裝置的具體實現方法。該方法將FPGA的普通I/O管腳構成一箇信號接口總線,通過讀取信號接口闆的I2C總線EEPROM保存的信息,來分配FPGA管腳的功能,從而實現接口信號的可擴展性,滿足閤併單元輸入輸齣信號靈活多變的需求。同時,FPGA實現瞭採樣值報文的接收,記錄報文接收時標,採樣值報文的生成與髮送以及模擬MII接口直接與PHY通信等功能。結果錶明,本測試裝置能準確反映閤併單元的數據同步精度、採樣值精度,具有較彊的實用價值。
동보채양측시포함료수거동보측시여채양치정학도측시량개방면,시합병단원최중요적지표지일。재분석료합병단원동보채양측시적현상여존재적기술난점적기출상,개소료일충기우실시Linux계통결합FPGA실시자계통、접구신호가확전적합병단원동보채양측시장치적구체실현방법。해방법장FPGA적보통I/O관각구성일개신호접구총선,통과독취신호접구판적I2C총선EEPROM보존적신식,래분배FPGA관각적공능,종이실현접구신호적가확전성,만족합병단원수입수출신호령활다변적수구。동시,FPGA실현료채양치보문적접수,기록보문접수시표,채양치보문적생성여발송이급모의MII접구직접여PHY통신등공능。결과표명,본측시장치능준학반영합병단원적수거동보정도、채양치정도,구유교강적실용개치。
Synchronous sampling test contains data synchronization test and sample value accuracy test, which is one of the most important indicators of the merging unit. The status quo of the merging unit synchronous sampling test and technical difficulties are firstly analyzed, and then a specific implementation method of the merging unit synchronous sampling test device based on real-time Linux system, real-time FPGA subsystem and scalable interface signals is introduced. In order to achieve the scalability of the interface and meet the merging unit’s flexible input and output signals demand, this method uses FPGA I/O pins to construct a signal interface bus and assign FPGA pin functions through reading information saved by I2C bus EEPROM in the signal interface board. Also, this method realizes many functions like sample values receiving, time scale recording, sample values generating and transmitting, and simulating the direct communication between MII interface and the PHY in single chip FPGA. The results show that the test device can accurately reflect the synchronous sampling accuracy and data synchronization of the merging unit, so it has a strong practical value.