电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2013年
12期
26-29
,共4页
柳龙华%杜丽军%解启林%邱颖霞
柳龍華%杜麗軍%解啟林%邱穎霞
류룡화%두려군%해계림%구영하
共面波导%两位延迟线%薄膜电路
共麵波導%兩位延遲線%薄膜電路
공면파도%량위연지선%박막전로
coplanar waveguide%2 bits true-time delay line%thin film hybrid circuit
基于薄膜电路工艺制作的共面波导延迟线不仅具有体积小、重量轻、损耗低、抗干扰性强等优点,还易与其他微波电路集成,延时精度较准。但它对高精度、密集孔薄膜电路的制作提出了更高的要求。通过优化薄膜电路制作工艺流程,研制出图形精度优于±5μm,具有良好金属化通孔的X波段两位延迟线薄膜电路。测试结果显示,该X波段两位延迟线的插入损耗为-5.7 dB ~-4.6 dB,带内起伏优于±0.3 dB,中心频率点相位偏差为±5°,满足设计要求。
基于薄膜電路工藝製作的共麵波導延遲線不僅具有體積小、重量輕、損耗低、抗榦擾性彊等優點,還易與其他微波電路集成,延時精度較準。但它對高精度、密集孔薄膜電路的製作提齣瞭更高的要求。通過優化薄膜電路製作工藝流程,研製齣圖形精度優于±5μm,具有良好金屬化通孔的X波段兩位延遲線薄膜電路。測試結果顯示,該X波段兩位延遲線的插入損耗為-5.7 dB ~-4.6 dB,帶內起伏優于±0.3 dB,中心頻率點相位偏差為±5°,滿足設計要求。
기우박막전로공예제작적공면파도연지선불부구유체적소、중량경、손모저、항간우성강등우점,환역여기타미파전로집성,연시정도교준。단타대고정도、밀집공박막전로적제작제출료경고적요구。통과우화박막전로제작공예류정,연제출도형정도우우±5μm,구유량호금속화통공적X파단량위연지선박막전로。측시결과현시,해X파단량위연지선적삽입손모위-5.7 dB ~-4.6 dB,대내기복우우±0.3 dB,중심빈솔점상위편차위±5°,만족설계요구。
The coplanar waveguide true-time delay line, which is fabricated by thin film hybrid circuit’ s process, has several advantages such as small volume, light weight, low insert loss, and high anti-interference. It also can integrate with other microwave circuits conveniently, and the precision of true-time delay is exactly. Certainly, the fabrication of thin film hybrid circuit with high precision pattern and denseness vias process is more difficult. Through optimize the fabrication process, an X-band 2 bits true-time delay line thin film circuits has been fabricated. The microstrip precision is better than ±5μm. As show by the test results, the insert loss of 2 bits true-time delay line is-5.7dB~-4.6dB, the in-band loss variation is less than ±0.3dB, and the phase bias at operating frequencies is ±5 degree.