CAJ | 학술논문

设计了一种新的低压、高速、高线性度的双通道 MOS 开关栅压自举电路，该电路采用同时自举NMOS 和 PMOS 的并行结构，不但降低了 MOS 开关的导通电阻值，同时在输入信号的全摆幅范围内实现了常数的导通电阻；考虑了器件可靠性要求且与标准的 CMOS 工艺技术兼容．采用0.13μm CMOS 工艺和1.2 V 工作电压的仿真实验表明，提出开关的导通电阻在全摆幅输入信号范围内的变化量小于4.3％；在采样频率为100 M Hz ，输入峰峰值为1 V ，输入频率为100 M Hz时，提出开关的总谐波失真达到-88．33 dB ，较之传统的 NMOS 自举开关以及标准的 CMOS 传输门开关，分别提高了约-14.8 dB 和-29 dB ．设计的开关可应用于低压、高速高精度的开关电容电路中．
설계료일충신적저압、고속、고선성도적쌍통도 MOS 개관책압자거전로，해전로채용동시자거NMOS 화 PMOS 적병행결구，불단강저료 MOS 개관적도통전조치，동시재수입신호적전파폭범위내실현료상수적도통전조；고필료기건가고성요구차여표준적 CMOS 공예기술겸용．채용0.13μm CMOS 공예화1.2 V 공작전압적방진실험표명，제출개관적도통전조재전파폭수입신호범위내적변화량소우4.3％；재채양빈솔위100 M Hz ，수입봉봉치위1 V ，수입빈솔위100 M Hz시，제출개관적총해파실진체도-88．33 dB ，교지전통적 NMOS 자거개관이급표준적 CMOS 전수문개관，분별제고료약-14.8 dB 화-29 dB ．설계적개관가응용우저압、고속고정도적개관전용전로중．
A novel low-voltage , high-speed and high-linear dual-channel MOS bootstrapped switch is proposed . This proposed switch utilizes the bootstrapping technique of both NMOS and PMOS simultaneously , thus resulting in small-variation low-value on-resistance over the entire input signal range . The switch considers reliability constrains and is suitable for standard CMOS technology . Based on the 0.13 μm CMOS technology and 1.2 V power supply , simulation results show that the switch achieves an on-resistance variation less than 4.3% throughout the full range (V pp = 1 V )of the input signal range . For a 100 M Hz input with 1 V ( V pp ) amplitude , the switch has a total harmonic distortion ( T HD ) up to- 88.33 dB at the 100 M Hz sampling frequency , about - 14.8 dB and - 29 dB increase , compared with the conventional bootstrapped NMOS switch and the standard CMOS transmission gate , respectively . The circuit could be applied to the low-voltage and high speed-resolution switched-capacitor circuits .