华南理工大学学报(自然科学版)
華南理工大學學報(自然科學版)
화남리공대학학보(자연과학판)
JOURNAL OF SOUTH CHINA UNIVERSITY OF TECHNOLOGY(NATURAL SCIENCE EDITION)
2014年
3期
27-34
,共8页
乘法器%冗余%逻辑设计%解码%计算方法
乘法器%冗餘%邏輯設計%解碼%計算方法
승법기%용여%라집설계%해마%계산방법
multiplier%redundancy%logic design%encoding%computational method
为提高定点乘法器速度,减少乘法器面积,基于Radix-16冗余并行乘法器,将奇数倍部分积用冗余差分形式表示;将部分积的修正位与部分积进行压缩,减少了部分积数量;通过优化控制信号产生电路、Booth解码电路和二进制转换电路的结构,进一步减少了乘法器延时和面积。 TSMC 180 nm工艺下的Design Complier综合结果表明,改进后冗余乘法器的面积相对减少8%,延时相对减少11%。
為提高定點乘法器速度,減少乘法器麵積,基于Radix-16冗餘併行乘法器,將奇數倍部分積用冗餘差分形式錶示;將部分積的脩正位與部分積進行壓縮,減少瞭部分積數量;通過優化控製信號產生電路、Booth解碼電路和二進製轉換電路的結構,進一步減少瞭乘法器延時和麵積。 TSMC 180 nm工藝下的Design Complier綜閤結果錶明,改進後冗餘乘法器的麵積相對減少8%,延時相對減少11%。
위제고정점승법기속도,감소승법기면적,기우Radix-16용여병행승법기,장기수배부분적용용여차분형식표시;장부분적적수정위여부분적진행압축,감소료부분적수량;통과우화공제신호산생전로、Booth해마전로화이진제전환전로적결구,진일보감소료승법기연시화면적。 TSMC 180 nm공예하적Design Complier종합결과표명,개진후용여승법기적면적상대감소8%,연시상대감소11%。
In order to improve the speed and reduce the area of fixed-point multipliers,odd multiple of partial products is represented with the redundant differential based on the Radix-16 redundant parallel multiplier. Then, the correction words of partial products and the partial products are compressed to reduce the number of partial products. Through optimizing the structures of the control signal generator,the Booth decoder and the binary con-verter,the time delay and the area of the multiplier are further reduced. Finally,the modified multiplier is synthe-sized by Design Complier with the TSMC 180nm library,with an area decrement of 8% and a delay reduction of 11% being obtained.