CAJ | 학술논문

设计了一种带自刷新功能的寄存器，该寄存器采用两级数据锁存结构，在第二级锁存结构中设计了一个选择电路。该选择电路采用三选二机制，用于三模冗余结构中取代常用寄存器，选择数据来自三模冗余结构的三路输出。有两路值相同，输出结果为该值，用于修正寄存器的输出值。在0.13μm工艺条件下用此结构设计的寄存器，面积为32.4μm×8.4μm，动态功耗0.072μW·MHz-1，建立时间0.1 ns，保持时间0.08 ns。该结构用于三模冗余结构中，可有效防止单粒子翻转效应（Single Event Upset, SEU）的发生。测试结果表明采用该结构的寄存器组成的存储单元三模冗余加固结构，在时钟频率1 GHz时，单粒子翻转错误率小于10-5。
설계료일충대자쇄신공능적기존기，해기존기채용량급수거쇄존결구，재제이급쇄존결구중설계료일개선택전로。해선택전로채용삼선이궤제，용우삼모용여결구중취대상용기존기，선택수거래자삼모용여결구적삼로수출。유량로치상동，수출결과위해치，용우수정기존기적수출치。재0.13μm공예조건하용차결구설계적기존기，면적위32.4μm×8.4μm，동태공모0.072μW·MHz-1，건립시간0.1 ns，보지시간0.08 ns。해결구용우삼모용여결구중，가유효방지단입자번전효응（Single Event Upset, SEU）적발생。측시결과표명채용해결구적기존기조성적존저단원삼모용여가고결구，재시종빈솔1 GHz시，단입자번전착오솔소우10-5。
Designed a self-relfesh lfip-lfop which structure has two data latches and a voter circuit is added to the second stage latch. The function of the voter is to output the logic value that corresponds to at least two of its inputs. The new lfip-lfop can be used to the circuit of triple module redundancy to instead of normal lfip-lfop. It fabricated in 0.13μm standard CMOS process occupies a die area of 32.4μm×8.4μm, the dynamic power consumption was 0.072μW·MHz-1, the setup time is 0.1 ns, and the hold time is 0.08 ns. This structure was applied to Triple Module Redundancy can efifciently prevent Single Event Upset, and Experiment results show that Single-Event Effect Error rate lower than 10-5.