无线电通信技术
無線電通信技術
무선전통신기술
RADIO COMMUNICATIONS TECHNOLOGY
2012年
6期
52-55
,共4页
高速%分相位%逻辑综合%动态仿真
高速%分相位%邏輯綜閤%動態倣真
고속%분상위%라집종합%동태방진
high-speed%multi-phase%logic synthesis%dynamic simulation
高速的数模混合电路设计通常要求对模拟信号产生的数据进行实时准确采样。介绍了基于分相位时钟组的高速数据采样电路，并手工设计一款高性能锁相环和延时锁相环来产生数字电路时钟组，加载特定的逻辑综合约束，最终使用动态仿真工具进行电路仿真。仿真结果表明在使用分相位时钟组实现高速数据采样的同时，还可以有效地改善时序和布局布线的压力。
高速的數模混閤電路設計通常要求對模擬信號產生的數據進行實時準確採樣。介紹瞭基于分相位時鐘組的高速數據採樣電路，併手工設計一款高性能鎖相環和延時鎖相環來產生數字電路時鐘組，加載特定的邏輯綜閤約束，最終使用動態倣真工具進行電路倣真。倣真結果錶明在使用分相位時鐘組實現高速數據採樣的同時，還可以有效地改善時序和佈跼佈線的壓力。
고속적수모혼합전로설계통상요구대모의신호산생적수거진행실시준학채양。개소료기우분상위시종조적고속수거채양전로，병수공설계일관고성능쇄상배화연시쇄상배래산생수자전로시종조，가재특정적라집종합약속，최종사용동태방진공구진행전로방진。방진결과표명재사용분상위시종조실현고속수거채양적동시，환가이유효지개선시서화포국포선적압력。
High-speed mix of digital and analog circuits should accurately sample the data which is produced by the analog circuits in real time. High-speed data sampling can be solved by the multi -phase clocks. In the physical design stage,the clock sources can be provided by high-performance phase locked loop and delayed phase locked loop which are designed manually; in the logic synthesis stage, the clock constrains are consistent ,and the group clock can be simulated by the dynamic simulation tools in multi-models. The time sequence can be improved and the pressure of layout wiring can be mitigated effectively by the multi-phase clocks.
