CAJ | 학술논문

针对Ahera公司SOPC解决方案中，DMA模块无法直接读／写FPGA外设的情况，提出了基于Avalon总线流传输模式的通用DMA读／写控制模块的设计，设计了两个自定义外设，实现了DMA对FPGA外设的高速数据存取和NiosII与FPGA大批量数据的快速传输。介绍了Avalon—MM总线规范，阐述了系统架构以及DMA读控制器的设计，测试结果表明，该方法是一种高效可行的解决方案。
침대Ahera공사SOPC해결방안중，DMA모괴무법직접독／사FPGA외설적정황，제출료기우Avalon총선류전수모식적통용DMA독／사공제모괴적설계，설계료량개자정의외설，실현료DMA대FPGA외설적고속수거존취화NiosII여FPGA대비량수거적쾌속전수。개소료Avalon—MM총선규범，천술료계통가구이급DMA독공제기적설계，측시결과표명，해방법시일충고효가행적해결방안。
In view of the fact that DMA module can not read/write FPGA peripherals directly in SOPC solutions of Ahera company, this paper puts forward the design of general DMA read/write control module based on the trans- mission mode of Avalon bus flow. The design of two custom peripherals makes it possible for DMA to access High- speed data of FPGA peripherals. It implements rapid transmission of bulk data between the Nios II and FPGA. The paper briefly introduces the Avalon-MM bus norms, and elaborates the design of system architecture and read control- ler of DMA. Finally the test results show that the solution is efficient and feasible.