CAJ | 학술논문

设计了一种基于源级耦合结构的正交二分频电路，由两个完全相同的源级耦合D触发器级联构成，交替工作于触发和锁存模式。对传统的源级耦合结构做了适当改进，采用动态负载，通过对PMOS管的开：是控制很好地解决了电路工作速度和输出摆幅间的矛盾；且时钟开关PMOS和NMOS采用不同直流偏置，便于低电源电压下直流工作点的选取。采用TSMC 0．18μmRFCMOS工艺进行仿真验证。实验结果表明，分频器在1．92GHz愉入时钟频率下能正常实现正交二分频，有较宽的锁定范围，且在3V电源电压下功耗仅为1．15mW。
설계료일충기우원급우합결구적정교이분빈전로，유량개완전상동적원급우합D촉발기급련구성，교체공작우촉발화쇄존모식。대전통적원급우합결구주료괄당개진，채용동태부재，통과대PMOS관적개：시공제흔호지해결료전로공작속도화수출파폭간적모순；차시종개관PMOS화NMOS채용불동직류편치，편우저전원전압하직류공작점적선취。채용TSMC 0．18μmRFCMOS공예진행방진험증。실험결과표명，분빈기재1．92GHz유입시종빈솔하능정상실현정교이분빈，유교관적쇄정범위，차재3V전원전압하공모부위1．15mW。
A quadrature frequency divider based on source-coupled-logic is presented in this paper, and designed in TSMC 0.18 μm IIF CMOS leehnology. It eonsists two identical and mutually coupled flip-flops or latches which operate alternatively in flip-ping and la',ehed modes at the clock frequency. In this paper, we adopt dynamic load which shall ideally be small during flipping yet large while latched. This carl keep the RC time constant small and make the signal difference large. Also tile PMOS and NMOS switch-es use different bias, that earl be easier to make a exact DC point. The circuit is designed in TSMC 0.18 μm RF CMOS process and dissipates an power of 1.15 mW from a 3 V supply. It can work at 1.92 GHz normally, and has a wide locking range.