CAJ | 학술논문

为了在解映射过程中尽量减少锁相环的使用，设计了一种基于同步时钟产生的均匀缺口时钟来实现解帧、去 FEC(前向纠错)以及 OTU2(光传输单元)解映射到 ODU2(光数据单元)的同步电路。通过仿真和 FPGA(现场可编程门阵列)验证了该电路功能的正确性。结果表明，该电路能够实时、准确地完成 OTU2到 ODU2的解映射。
위료재해영사과정중진량감소쇄상배적사용，설계료일충기우동보시종산생적균균결구시종래실현해정、거 FEC(전향규착)이급 OTU2(광전수단원)해영사도 ODU2(광수거단원)적동보전로。통과방진화 FPGA(현장가편정문진렬)험증료해전로공능적정학성。결과표명，해전로능구실시、준학지완성 OTU2도 ODU2적해영사。
In order to reduce the use of PLL as much as possible in the process of demapping,this paper designs a sync circuit. On the basis of the uniform gaps in the clock produced by a sync clock,the sync circuit is used to realize deframing,de-FEC and demapping from OTU2 to ODU2.Simulation and FPGA test results verify the correctness of the circuit functions,indica-ting that this circuit can accomplish demapping from OTU2 to ODU2 in real-time and accurately.