电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2014年
5期
28-32
,共5页
数据Cache%重装控制%Line Buffer
數據Cache%重裝控製%Line Buffer
수거Cache%중장공제%Line Buffer
DSP%data-cache%reifll%line-buffer
Cache能够提高DSP处理器对外部存储器的存取速度，提高DSP的性能，设计高性能低功耗的Cache，对于提高DSP芯片的整体性能有着十分重大的意义。描述了DSP芯片中一种高性能低功耗的数据Cache。这种Cache可以通过增加具备重装功能的Line Buffer来减少处理器对Cache的访问频率，从而降低Cache功耗。通过FFT、AC3、FIR三种基准程序测试表明，Line Buffer可以降低35%的Cache访问频率，明显降低了数据Cache功耗。
Cache能夠提高DSP處理器對外部存儲器的存取速度，提高DSP的性能，設計高性能低功耗的Cache，對于提高DSP芯片的整體性能有著十分重大的意義。描述瞭DSP芯片中一種高性能低功耗的數據Cache。這種Cache可以通過增加具備重裝功能的Line Buffer來減少處理器對Cache的訪問頻率，從而降低Cache功耗。通過FFT、AC3、FIR三種基準程序測試錶明，Line Buffer可以降低35%的Cache訪問頻率，明顯降低瞭數據Cache功耗。
Cache능구제고DSP처리기대외부존저기적존취속도，제고DSP적성능，설계고성능저공모적Cache，대우제고DSP심편적정체성능유착십분중대적의의。묘술료DSP심편중일충고성능저공모적수거Cache。저충Cache가이통과증가구비중장공능적Line Buffer래감소처리기대Cache적방문빈솔，종이강저Cache공모。통과FFT、AC3、FIR삼충기준정서측시표명，Line Buffer가이강저35%적Cache방문빈솔，명현강저료수거Cache공모。
Cache can speed up the access to memory from DSP processor and enhance DSP performance at the same time. Thus, to enhance the performance of the whole DSP processor, it is of great signiifcance to design a kind of cache that is of high performance and low power. The thesis describes the system architecture of data cache and function simulation of the cache. This kind of cache contains a line buffer to reduce the access frequency from the CPU to cache, so as to decrease the power consumption. By running three benchmarks including FFT AC3 and FIR, made a conclusion that the line buffer reduces the access frequency from DSP core to cache by 35%, obviously decreases power consumption of the data cache.
