电子与信息学报
電子與信息學報
전자여신식학보
JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY
2014年
6期
1504-1508
,共5页
薛茜男%李振%姜承翔%王鹏%田毅
薛茜男%李振%薑承翔%王鵬%田毅
설천남%리진%강승상%왕붕%전의
机载电子器件%单粒子翻转(SEU)%故障注入%抗辐射加固技术%FPGA
機載電子器件%單粒子翻轉(SEU)%故障註入%抗輻射加固技術%FPGA
궤재전자기건%단입자번전(SEU)%고장주입%항복사가고기술%FPGA
Airborne electronic device%Single Event Upset (SEU)%Fault injection%Radiation hardening technique%FPGA
随着新型电子器件越来越多地被机载航电设备所采用,单粒子翻转(Single Event Upset, SEU)故障已经成为影响航空飞行安全的重大隐患。首先,针对由于单粒子翻转故障的随机性,该文对不同时刻发生的单粒子翻转故障引入了多时钟控制,构建了SEU故障注入测试系统。然后模拟真实情况下单粒子效应引发的多时间点故障,研究了单粒子效应对基于FPGA构成的时序电路的影响,并在线统计了被测模块的失效数据和失效率。实验结果表明,对于基于FPGA构建容错电路,采用多时钟沿三模冗余(Triple Modular Redundancy, TMR)加固技术可比传统TMR技术提高约1.86倍的抗SEU性能;该多时钟SEU故障注入测试系统可以快速、准确、低成本地实现单粒子翻转故障测试,从而验证了SEU加固技术的有效性。
隨著新型電子器件越來越多地被機載航電設備所採用,單粒子翻轉(Single Event Upset, SEU)故障已經成為影響航空飛行安全的重大隱患。首先,針對由于單粒子翻轉故障的隨機性,該文對不同時刻髮生的單粒子翻轉故障引入瞭多時鐘控製,構建瞭SEU故障註入測試繫統。然後模擬真實情況下單粒子效應引髮的多時間點故障,研究瞭單粒子效應對基于FPGA構成的時序電路的影響,併在線統計瞭被測模塊的失效數據和失效率。實驗結果錶明,對于基于FPGA構建容錯電路,採用多時鐘沿三模冗餘(Triple Modular Redundancy, TMR)加固技術可比傳統TMR技術提高約1.86倍的抗SEU性能;該多時鐘SEU故障註入測試繫統可以快速、準確、低成本地實現單粒子翻轉故障測試,從而驗證瞭SEU加固技術的有效性。
수착신형전자기건월래월다지피궤재항전설비소채용,단입자번전(Single Event Upset, SEU)고장이경성위영향항공비행안전적중대은환。수선,침대유우단입자번전고장적수궤성,해문대불동시각발생적단입자번전고장인입료다시종공제,구건료SEU고장주입측시계통。연후모의진실정황하단입자효응인발적다시간점고장,연구료단입자효응대기우FPGA구성적시서전로적영향,병재선통계료피측모괴적실효수거화실효솔。실험결과표명,대우기우FPGA구건용착전로,채용다시종연삼모용여(Triple Modular Redundancy, TMR)가고기술가비전통TMR기술제고약1.86배적항SEU성능;해다시종SEU고장주입측시계통가이쾌속、준학、저성본지실현단입자번전고장측시,종이험증료SEU가고기술적유효성。
With the new electronic devices are increasingly used by airborne avionics equipment, Single Event Upset (SEU) fault has become a major hazard on aviation safety. Because of the randomness of SEU fault, the SEU fault occurs at any moments. Firstly, a multi-clock control is introduced to construct an SEU fault injection testing system. Secondly, the system simulates multi-time point of failure with real situations caused by single event upset effects. For sequential circuits constructed by SRAM-based FPGA, the influence of SEU is studied by the system and the failure data and failure rate of the undertest module is counted online. Two kinds of FPGA-based fault-tolerant circuit are tested by this system. Comparing with the traditional Triple Modular Redundancy (TMR) technology, the anti-SEU performance of the proposed multi-clock edge TMR reinforcement technology is improved about 1.86-fold. The experiment results verify that the proposed multi-clock SEU fault injection testing system is a quick, low-cost and highly accurate test for the single-event upsets fault, and demonstrate the effectiveness of the proposed SEU reinforcement technology.