CAJ | 학술논문

片上系统（SoC）是芯片设计的发展趋势，现场可编程门阵列（FPGA）验证是芯片设计中最重要的环节之一。基于Altera公司的FPGA和静态时序分析工具TimeQuest的应用，提出了一种使用两个或多个FPGA器件验证复杂SoC的方法，分析了使用多个FPGA器件进行功能验证对于SoC设计的重要性，介绍了FPGA时序约束的具体设置方式；并把这种方法应用在实例中，测试结果显示通过使用这种方式可以快速有效的实现对大规模、复杂时序SoC的功能验证。
편상계통（SoC）시심편설계적발전추세，현장가편정문진렬（FPGA）험증시심편설계중최중요적배절지일。기우Altera공사적FPGA화정태시서분석공구TimeQuest적응용，제출료일충사용량개혹다개FPGA기건험증복잡SoC적방법，분석료사용다개FPGA기건진행공능험증대우SoC설계적중요성，개소료FPGA시서약속적구체설치방식；병파저충방법응용재실례중，측시결과현시통과사용저충방식가이쾌속유효적실현대대규모、복잡시서SoC적공능험증。
System on Chip(SoC) is the trend in the development of integrated circuit. Verification is the important process for SoC design. Based on the applications of Field Programmable Gate Array (FPGA) and TimeQuest which is the STA tool of the Altera Corporation, the paper gives a method which uses two or more FPGA devices to validate complicated SoC, and analyzes the importance of the functional validation for SoC. The paper also introduces the material setting modes about the timing constraint and uses these methods in the practical example. The test results indicate these methods are fast and effective, and can be used to make the functional validation for large-scale and complicated time-sequence SoC.