CAJ | 학술논문

提出了一种有符号乘法器电路的编程语言，其核心思想是采用指令表示乘法器的编码器、加法器树、快速加法器等三个部分，然后经由指令描述互联关系形成乘法器．通过Lex/Yacc构成编译器，解析程序得到乘法器的Verilog代码．采用该设计语言生成的七种典型结构的32位有符号单周期乘法器，在200MHz工作频率设定下，使用GRACE 0.18μm 1P6M工艺，进行逻辑综合、布局布线、静态时序和功耗分析．实验结果表明，这七种乘法器速度都优于Synopsys Design Ware产生的乘法器，其中由改进型Booth Radix4编码、冗余二进制加法器树和跳跃进位加法器构成的乘法器综合性能超出Synopsys Design Ware产生的乘法器达35％，因此该设计语言可应用于高性能乘法器电路快速设计应用中．
제출료일충유부호승법기전로적편정어언，기핵심사상시채용지령표시승법기적편마기、가법기수、쾌속가법기등삼개부분，연후경유지령묘술호련관계형성승법기．통과Lex/Yacc구성편역기，해석정서득도승법기적Verilog대마．채용해설계어언생성적칠충전형결구적32위유부호단주기승법기，재200MHz공작빈솔설정하，사용GRACE 0.18μm 1P6M공예，진행라집종합、포국포선、정태시서화공모분석．실험결과표명，저칠충승법기속도도우우Synopsys Design Ware산생적승법기，기중유개진형Booth Radix4편마、용여이진제가법기수화도약진위가법기구성적승법기종합성능초출Synopsys Design Ware산생적승법기체35％，인차해설계어언가응용우고성능승법기전로쾌속설계응용중．
This paper presents a programming language for designing signed multiplier circuit .The key idea is using instruc-tion to express the encoding units ,addition tree units and fast adder units of multiplier ,and using the connection of instruction de-scription to obtain a multiplier .The multiplier of program through Lex and Yacc translate source code containing connection into Verilog code .Seven typical structures of 32 bits signed multipliers are obtained by the instruction description .Under 200MHz syn-thesis condition and in GRACE 0.18μm process ,these multipliers are run for logic synthesis ,placed and routed ,static timing analy-sis ,and power analysis .The experiment results suggest that the speeds of all the seven multipliers show advantage over that produced by Synopsys design ware ,and the multiplier performance composed of modified Booth Radix 4 encoding ,redundant binary addition tree and carry skip adder exceeds that produced by Synopsys design ware by 35% .Therefore ,this language can be used to the appli-cation of high performance multiplier design .