CAJ | 학술논문

设计一种低抖动电荷泵锁相环频率合成器，输出频率为400 MHz~1 GHz。电路采用电流型电荷泵自举结构消除电荷共享效应，同时实现可编程多种输出电流值。通过具体的频率范围来选择使用的VCO，获得更小的锁相环相位抖动。电路采用0.13μm 1.2 V CMOS工艺，芯片面积为0.6 mm×0.5 mm。Hsim后仿真结果显示当输出频率为1 GHz时，锁相环频率合成器的锁定时间为4.5μs，功耗为19.6 mW，最大周对周抖动为11 ps。
설계일충저두동전하빙쇄상배빈솔합성기，수출빈솔위400 MHz~1 GHz。전로채용전류형전하빙자거결구소제전하공향효응，동시실현가편정다충수출전류치。통과구체적빈솔범위래선택사용적VCO，획득경소적쇄상배상위두동。전로채용0.13μm 1.2 V CMOS공예，심편면적위0.6 mm×0.5 mm。Hsim후방진결과현시당수출빈솔위1 GHz시，쇄상배빈솔합성기적쇄정시간위4.5μs，공모위19.6 mW，최대주대주두동위11 ps。
A low-jitter charge pump phase-locked loop synthesizer with output frequency from 400 MHz to 1 GHz is designed. Charge sharing effect is eliminated by bootstrapping of current-steering charge pump, which can output multiple currents by programming. The VCO is chosen according to the specific frequency range to obtain lower jitter in PLL. The circuit is implemented in 0.13μm CMOS process and operates from 1.2 V supply. The chip area is about 0.6 mm×0.5 mm. The Hsim Post-Simulation results show that the locking time is 4.5μs, the power is 19.6 mW, and the maximum cycle to cycle jitter is 11 ps, when output frequency reaches 1 GHz.