CAJ | 학술논문

　　针对国内目前没有专门用于保证半导体集成电路芯片质量与可靠性要求的相关标准，相应测试、可靠性研究水平也较为落后的情况，对半导体集成电路芯片质量与可靠性保证方法进行研究。介绍半导体集成电路芯片质量与可靠性保证方面的国际、国内标准与技术水平现状，提出在目前技术水平下需从设计、工艺、筛选验证3个方面保证半导体集成电路芯片质量与可靠性，在筛选验证方面提出芯片筛选、封装样品考核相结合的方式。结果表明，该方法能满足混合集成电路、多芯片组件对半导体集成电路芯片的质量与可靠性要求。
　　침대국내목전몰유전문용우보증반도체집성전로심편질량여가고성요구적상관표준，상응측시、가고성연구수평야교위락후적정황，대반도체집성전로심편질량여가고성보증방법진행연구。개소반도체집성전로심편질량여가고성보증방면적국제、국내표준여기술수평현상，제출재목전기술수평하수종설계、공예、사선험증3개방면보증반도체집성전로심편질량여가고성，재사선험증방면제출심편사선、봉장양품고핵상결합적방식。결과표명，해방법능만족혼합집성전로、다심편조건대반도체집성전로심편적질량여가고성요구。
Aiming at the actuality that there have no standards to ensure the quality and reliability for semiconductor dies, the level of testing and reliability research is relatively behindhand, the paper states the methods to ensure the quality and reliability of semiconductor dies. The quality and reliability assurance standards and techniques for semiconductor dies are presented. The method to assure the quality and reliability from three aspects including design, technology, riddling and test are discussed in detail. Riddling is for all semiconductor dies, while, testing is for samples after packed. The results show that this method can meet the requirements for the quality and reliability of semiconductor dies used in HIC and MCM.