CAJ | 학술논문

　　在修正型Booth算法和Wallace树结构以及选择进位加法器的基础上，提出了一种新型32位单精度浮点乘法器结构。该新型结构通过截断选择进位加法器进位链，缩短了关键路径延时。传统选择进位加法器每一级加法器的进位选择来自上级的进位输出。提出的结构可以提前计算出尾数第16位的结果，它与Wallace树输出的相关位比较就可得出来自前一位的进位情况进而快速得到进位选择。在Altera的EP2C70F896C6器件上，基于该结构实现了一个支持IEEE754浮点标准的4级流水线浮点乘法器，时序仿真表明，该方法将传统浮点乘法器结构关键路径延时由6.4 ns减小到5.9 ns。
　　재수정형Booth산법화Wallace수결구이급선택진위가법기적기출상，제출료일충신형32위단정도부점승법기결구。해신형결구통과절단선택진위가법기진위련，축단료관건로경연시。전통선택진위가법기매일급가법기적진위선택래자상급적진위수출。제출적결구가이제전계산출미수제16위적결과，타여Wallace수수출적상관위비교취가득출래자전일위적진위정황진이쾌속득도진위선택。재Altera적EP2C70F896C6기건상，기우해결구실현료일개지지IEEE754부점표준적4급류수선부점승법기，시서방진표명，해방법장전통부점승법기결구관건로경연시유6.4 ns감소도5.9 ns。
On the basis of the modified Booth encoding,Wallace tree structure and carry-select adder,a new structure of 32-bit float point multiplier is proposed,which can shorten its critical path delay by cutting the carry chain. The carry selection of each level of the carry-select adder comes from the upper carry output. The new structure can produce the 16th bit of the man-tissa. By comparing it with the relative output bit of the Wallace tree,the carry which comes from the former bit can be got to achieve the carry selection. By using the new structure,a 4-stage pipeline float point multiplier supporting IEEE754 standard is implemented on Altera’s FPGA device EP2C70F896C6. The time-sequence simulation shows that the critical path delay of the multiplier is 5.9 ns,less than that of the traditional multiplier,which is 6.4 ns.