CAJ | 학술논문

闩锁效应是体硅CMOS电路中最为严重的失效机理之一，而且随着器件特征尺寸越来越小，使得CMOS电路结构中的闩锁效应日益突出。以P阱CMOS反相器和CMOS集成电路的工艺结构为基础，采用可控硅等效电路模型，较为详细地分析了闩锁效应的形成机理，并利用试验证实，通过加深P阱深度，可以明显提升CMOS电路的抗闩锁性能。
산쇄효응시체규CMOS전로중최위엄중적실효궤리지일，이차수착기건특정척촌월래월소，사득CMOS전로결구중적산쇄효응일익돌출。이P정CMOS반상기화CMOS집성전로적공예결구위기출，채용가공규등효전로모형，교위상세지분석료산쇄효응적형성궤리，병이용시험증실，통과가심P정심도，가이명현제승CMOS전로적항산쇄성능。
Latch-up effect is one of the most important failure mechanisms in CMOS IC with silicon substrate. And Latch-up in CMOS IC is stand out increasingly with device channel length becoming smaller and smaller. Based on CMOS inverter in P-well and the structure of CMOS IC process, SCR equivalent circuit model is adopted to analyze the mechanism of latch-up in detail. It is proved by experiments that latch up immunity of CMOS IC can be improved obviously by increase of P-well depth.