电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2014年
6期
18-22,31
,共6页
FPGA%单粒子翻转%软错误%结构建模%软错误评估
FPGA%單粒子翻轉%軟錯誤%結構建模%軟錯誤評估
FPGA%단입자번전%연착오%결구건모%연착오평고
FPGA%single event upset (SEU)%soft error%structural modeling%soft error assessment
FPGA器件在航天领域应用广泛，然而在空间环境下，基于SRAM工艺的FPGA器件极易受到单粒子翻转（Single Event Upsets，SEU）影响而导致电路发生软错误。针对具有代表性的Xilinx Virtex系列器件进行了SEU评估方法的研究，设计并开发了一款面向Virtex器件的SEU效应评估工具，并与FPGA标准设计流程进行了有效融合。实验结果表明，提出的评估方法和工具对Virtex器件的SEU效应可以进行准确的评估，从而为FPGA结构设计和应用开发提供先于硬件实现的软件验证环境，对高可靠性FPGA芯片的研究、开发和设计都具有重要意义。
FPGA器件在航天領域應用廣汎，然而在空間環境下，基于SRAM工藝的FPGA器件極易受到單粒子翻轉（Single Event Upsets，SEU）影響而導緻電路髮生軟錯誤。針對具有代錶性的Xilinx Virtex繫列器件進行瞭SEU評估方法的研究，設計併開髮瞭一款麵嚮Virtex器件的SEU效應評估工具，併與FPGA標準設計流程進行瞭有效融閤。實驗結果錶明，提齣的評估方法和工具對Virtex器件的SEU效應可以進行準確的評估，從而為FPGA結構設計和應用開髮提供先于硬件實現的軟件驗證環境，對高可靠性FPGA芯片的研究、開髮和設計都具有重要意義。
FPGA기건재항천영역응용엄범，연이재공간배경하，기우SRAM공예적FPGA기건겁역수도단입자번전（Single Event Upsets，SEU）영향이도치전로발생연착오。침대구유대표성적Xilinx Virtex계렬기건진행료SEU평고방법적연구，설계병개발료일관면향Virtex기건적SEU효응평고공구，병여FPGA표준설계류정진행료유효융합。실험결과표명，제출적평고방법화공구대Virtex기건적SEU효응가이진행준학적평고，종이위FPGA결구설계화응용개발제공선우경건실현적연건험증배경，대고가고성FPGA심편적연구、개발화설계도구유중요의의。
FPGA Devices are widely used in aerospace applications, while soft errors that caused by SEU (Single Event Upset) are easily happening to SRAM-based FPGA devices in the space environment. The paper studied the method of SEU assessment which is aimed at the typical Xilinx Virtex series devices, then designed and developed a Virtex-devices-oriented SEU assessing tool, and further provided the interface to the standard FPGA designing flow. Shown by the experiment, that the method and the tool of the paper are able to exactly assess the effect of SEU upon Virtex devices. The paper provided a software verification environment that precedes the hardware implementations, which is significant in the studying, designing and developing of highly reliable FPGA devises.
