现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2014年
13期
153-155,158
,共4页
带隙基准电压%低功耗%电源抑制%电路设计
帶隙基準電壓%低功耗%電源抑製%電路設計
대극기준전압%저공모%전원억제%전로설계
bandgap reference voltage%low-power consumption%power supply rejection%circuit design
为了降低芯片电路功耗，电源电压需要不断的减小，这将导致电源噪声对基准电压产生严重影响。为此针对这一问题进行相关研究，采用SMIC 0.18μm工艺，设计出一种低功耗、低温度系数的高PSR带隙基准电压源。仿真结果表明，该设计带隙基准源的PSR在50 kHz与100 kHz分别为-65.13 dB和-53.85 dB；在2~6 V电源电压下，工作电流为30μA，温度系数为30.38 ppm/℃，电压调整率为71.47μV/V。该带隙基准适用于在低功耗高PSR性能需求的LDOs电路中应用。
為瞭降低芯片電路功耗，電源電壓需要不斷的減小，這將導緻電源譟聲對基準電壓產生嚴重影響。為此針對這一問題進行相關研究，採用SMIC 0.18μm工藝，設計齣一種低功耗、低溫度繫數的高PSR帶隙基準電壓源。倣真結果錶明，該設計帶隙基準源的PSR在50 kHz與100 kHz分彆為-65.13 dB和-53.85 dB；在2~6 V電源電壓下，工作電流為30μA，溫度繫數為30.38 ppm/℃，電壓調整率為71.47μV/V。該帶隙基準適用于在低功耗高PSR性能需求的LDOs電路中應用。
위료강저심편전로공모，전원전압수요불단적감소，저장도치전원조성대기준전압산생엄중영향。위차침대저일문제진행상관연구，채용SMIC 0.18μm공예，설계출일충저공모、저온도계수적고PSR대극기준전압원。방진결과표명，해설계대극기준원적PSR재50 kHz여100 kHz분별위-65.13 dB화-53.85 dB；재2~6 V전원전압하，공작전류위30μA，온도계수위30.38 ppm/℃，전압조정솔위71.47μV/V。해대극기준괄용우재저공모고PSR성능수구적LDOs전로중응용。
The power supply voltage needs to be constantly decreased to meet the requirement of reducing the low-power consumption of IC,but it may lead to the negative impact of power supply noise on the reference voltage. A low-power consump-tion bandgap voltage reference with high PSR (power supply rejection) and low-temperature coefficent was design based on in SMIC0.18μm process. The simulation results show that the PSR of the bandgap reference source is -65.13 dB at 50 kHz and -53.85 dB at 100 kHz respectively;at 2~6 V supply voltage,the supply current is 30 μA,the temperature coefficient is 30.38 ppm/℃,and the voltage regulation rate is 71.47 μV/V. The bandgap voltage reference is suitable for LDOs circuit which has the requirements of low-power consumption and high PSR.
