计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2014年
7期
1-7
,共7页
黄睿%杨庆庆%程洁琼%周晓方
黃睿%楊慶慶%程潔瓊%週曉方
황예%양경경%정길경%주효방
专用控制器%解码器%流水线划分%加速器%存储器划分%LDPC码%Turbo码
專用控製器%解碼器%流水線劃分%加速器%存儲器劃分%LDPC碼%Turbo碼
전용공제기%해마기%류수선화분%가속기%존저기화분%LDPC마%Turbo마
Application Specific Control Processor(ASCP)%decoder%pipeline partition%accelerator%memory partition%Low Density Parity Check(LDPC) code%Turbo code
对于兼容 LDPC和 Turbo 码的多模通信信道解码器,解码过程涉及大量数据计算和传输,系统高吞吐率的实时性要求使这类多模解码器的结构变得日益复杂。为此,设计并实现一种专用控制器,对待解码数据进行预处理,以控制整个解码器系统的工作。为满足解码器系统高时钟频率、大量专用运算和数据快速传输3个要求,采用重划分控制器流水线、增加专用指令及加速器和片内存储器划分3种方法,使解码器系统最大程度地实现并行化计算处理。测试结果表明,在专用控制器的控制协调下,解码器能满足LTE标准1 Gb/s和UMTS标准672 Mb/s的高吞吐率要求。使用TSMC 65 nm低功耗库,通过后端布局进行布线设计后,该解码器面积约为490000μm2,最大时钟频率为540 MHz。
對于兼容 LDPC和 Turbo 碼的多模通信信道解碼器,解碼過程涉及大量數據計算和傳輸,繫統高吞吐率的實時性要求使這類多模解碼器的結構變得日益複雜。為此,設計併實現一種專用控製器,對待解碼數據進行預處理,以控製整箇解碼器繫統的工作。為滿足解碼器繫統高時鐘頻率、大量專用運算和數據快速傳輸3箇要求,採用重劃分控製器流水線、增加專用指令及加速器和片內存儲器劃分3種方法,使解碼器繫統最大程度地實現併行化計算處理。測試結果錶明,在專用控製器的控製協調下,解碼器能滿足LTE標準1 Gb/s和UMTS標準672 Mb/s的高吞吐率要求。使用TSMC 65 nm低功耗庫,通過後耑佈跼進行佈線設計後,該解碼器麵積約為490000μm2,最大時鐘頻率為540 MHz。
대우겸용 LDPC화 Turbo 마적다모통신신도해마기,해마과정섭급대량수거계산화전수,계통고탄토솔적실시성요구사저류다모해마기적결구변득일익복잡。위차,설계병실현일충전용공제기,대대해마수거진행예처리,이공제정개해마기계통적공작。위만족해마기계통고시종빈솔、대량전용운산화수거쾌속전수3개요구,채용중화분공제기류수선、증가전용지령급가속기화편내존저기화분3충방법,사해마기계통최대정도지실현병행화계산처리。측시결과표명,재전용공제기적공제협조하,해마기능만족LTE표준1 Gb/s화UMTS표준672 Mb/s적고탄토솔요구。사용TSMC 65 nm저공모고,통과후단포국진행포선설계후,해해마기면적약위490000μm2,최대시종빈솔위540 MHz。
There are a lot of calculations and data transmitting in the flexible Low Density Parity Check(LDPC) code and Turbo channel decoder. In order to meet the high throughput requirement, the decoder becomes more and more complicated. To solve this problem, an Application Specific Control Processor(ASCP) is proposed which pre-calculates the encoded data and controls the work of the whole decoder system. This high output decoder has three requirements for the control processor: high clock frequency, massive specific calculations and massive data transmitting. By designing the processor’s pipeline, application specific instruction sets, accelerators and memory structure, the decoder can run at a high paralleled status. As a result, the decoder can meet the high throughput requirement of LTE standard 1 Gb/s and UMTS standard 672 Mb/s. The placement and routing result is 490 000 μm2 with clock frequency 540 MHz using TSMC 65 nm low power lib and backend layout wiring.