计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2014年
7期
242-246
,共5页
直接数字波形合成%存储结构%自适应%并行重构器%现场可编程门阵列%综合后仿真%输出精度
直接數字波形閤成%存儲結構%自適應%併行重構器%現場可編程門陣列%綜閤後倣真%輸齣精度
직접수자파형합성%존저결구%자괄응%병행중구기%현장가편정문진렬%종합후방진%수출정도
Direct Digital Waveform Synthesis(DDWS)%storage structure%adaptive%parallel re-constructor%Field Programmable Gate Array(FPGA)%post syntheses simulation%output accuracy
直接数字波形合成(DDWS)可以最大程度保证信号的细节不遗漏，是模拟不规则波形的主要技术手段。现有DDWS存储结构虽然能解决速度性能与存储空间之间的矛盾，但是周期采样数必须是并行通道数的整数倍，限制了信号的输出精度。针对该问题，提出一种存储结构改进方法。通过研究波形数据输出序列的规律，改进地址发生器，对并行输出数据进行自适应选择，增加并行重构器，实现并行数据自适应排序。在现场可编程门阵列(FPGA)平台上进行综合后仿真验证，结果表明，该方法能克服周期采样数受限的不足，提高信号的输出精度，且逻辑增量小于FPGA总逻辑资源的1%，在硬件资源上具有明显优势。
直接數字波形閤成(DDWS)可以最大程度保證信號的細節不遺漏，是模擬不規則波形的主要技術手段。現有DDWS存儲結構雖然能解決速度性能與存儲空間之間的矛盾，但是週期採樣數必鬚是併行通道數的整數倍，限製瞭信號的輸齣精度。針對該問題，提齣一種存儲結構改進方法。通過研究波形數據輸齣序列的規律，改進地阯髮生器，對併行輸齣數據進行自適應選擇，增加併行重構器，實現併行數據自適應排序。在現場可編程門陣列(FPGA)平檯上進行綜閤後倣真驗證，結果錶明，該方法能剋服週期採樣數受限的不足，提高信號的輸齣精度，且邏輯增量小于FPGA總邏輯資源的1%，在硬件資源上具有明顯優勢。
직접수자파형합성(DDWS)가이최대정도보증신호적세절불유루，시모의불규칙파형적주요기술수단。현유DDWS존저결구수연능해결속도성능여존저공간지간적모순，단시주기채양수필수시병행통도수적정수배，한제료신호적수출정도。침대해문제，제출일충존저결구개진방법。통과연구파형수거수출서렬적규률，개진지지발생기，대병행수출수거진행자괄응선택，증가병행중구기，실현병행수거자괄응배서。재현장가편정문진렬(FPGA)평태상진행종합후방진험증，결과표명，해방법능극복주기채양수수한적불족，제고신호적수출정도，차라집증량소우FPGA총라집자원적1%，재경건자원상구유명현우세。
Direct Digital Waveform Synthesis(DDWS), which can ensure the greatest degree of signal details are not missed, is a main method to generate irregular waveform. Though existing memory structure in DDWS is able to overcome the contradiction between high-speed quality and memory space, the number of sampling must be multiples of the number of channel, which restricts the signal accuracy. To solve this problem, a method of memory structure is proposed. Though the study of the principle in the waveform output sequence, adaptive selection of parallel output data is implemented by modifying the address generators, adaptive sorting of parallel output data is implemented by adding parallel re-constructor. Through simulation and verification on Field Programmable Gate Array(FPGA), the results indicate that the restriction on the number of sampling is overcome and output accuracy of the signal is improved. By analyzing the resource dissipation, the overhead increment of logic resources is less than 1%of total logic resources in FPGA, which has a significant advantage on the hardware resources.
