CAJ | 학술논문

提出了一种基于伪随机补偿技术的流水线模数转换器（ADC）子级电路．该子级电路能够对比较器失调和电容失配误差进行实时动态补偿．误差补偿采用伪随机序列控制比较器阵列中参考比较电压的方式实现．比较器的高低位被随机分配，以消除各比较器固有失调对量化精度的影响，同时子ADC输出的温度计码具有伪随机特性，可进一步消除MDAC电容失配误差对余量输出的影响．基于该子级电路设计了一种12位250 MS/s流水线ADC，电路采用0．18μm 1P5M 1．8 V CMOS工艺实现，面积为2．5 mm2．测试结果表明，该ADC在全速采样条件下对20 MHz输入信号的信噪比（SNR）为69．92 dB，无杂散动态范围（SFDR）为81．17 dB，积分非线性误差（INL）为-0．4～＋0．65 LSB，微分非线性误差（DNL）为-0．2～＋0．15 LSB，功耗为320 mW．
제출료일충기우위수궤보상기술적류수선모수전환기（ADC）자급전로．해자급전로능구대비교기실조화전용실배오차진행실시동태보상．오차보상채용위수궤서렬공제비교기진렬중삼고비교전압적방식실현．비교기적고저위피수궤분배，이소제각비교기고유실조대양화정도적영향，동시자ADC수출적온도계마구유위수궤특성，가진일보소제MDAC전용실배오차대여량수출적영향．기우해자급전로설계료일충12위250 MS/s류수선ADC，전로채용0．18μm 1P5M 1．8 V CMOS공예실현，면적위2．5 mm2．측시결과표명，해ADC재전속채양조건하대20 MHz수입신호적신조비（SNR）위69．92 dB，무잡산동태범위（SFDR）위81．17 dB，적분비선성오차（INL）위-0．4～＋0．65 LSB，미분비선성오차（DNL）위-0．2～＋0．15 LSB，공모위320 mW．
A sub-stage circuit with pseudorandom sequences compensation for pipelined ADC (ana-log to digital converter)is presented.Comparator offset and capacitor mismatch error can be com-pensated dynamically in the sub-stage circuit.Compensation is achieved by controlling the reference voltages in sub-ADC using pseudorandom sequences.MSBs (most significant bits)and LSBs (least significant bits)of comparators are assigned randomly;accordingly,the influence of the offset of comparators on ADC quantization is eliminated.Pseudo-random thermometer code from the sub-ADC cancels the effect of the mismatches of MDAC (multiple digital to analog converter)capacitors on residue output.A 12-bit 250 MS/s pipelined ADC based on the proposed sub-stage circuit is pres-ented.This ADC is implemented in 0.18 μm 1P5M 1.8 V CMOS (complementary metal oxide semiconductor)process,with a die area of 2 .5 mm2 .Test results show that the ADC achieves an SNR(signal to noise ratio)of 69.92 dB,an SFDR(spurious-free dynamic range)of 81.17 dB,an INL(integral nonlinearity error)of -0.4 to +0.65 LSB,a DNL (differential nonlinearity error)of-0.2 to +0.15 LSB and a power consumption of 320 mW,for 20 MHz input at full sampling speed.