电子设计工程
電子設計工程
전자설계공정
ELECTRONIC DESIGN ENGINEERING
2014年
12期
41-44
,共4页
振动信号采集%数据流控制%时钟时标%FPGA
振動信號採集%數據流控製%時鐘時標%FPGA
진동신호채집%수거류공제%시종시표%FPGA
vibration signal acquisition%data flow management methods%clock time mark%FPGA
在振动信号采集和处理系统设计中,信号的处理时间与可靠性决定着系统应用的可行性。本文设计了一种基于FPGA的振动信号采集处理系统,该系统通过振动信号采集电路、抗混叠滤波电路、AD采样电路将电荷信号转化为数字信号送入FPGA,在FPGA处理设计中利用数据流控制方法并行实现了信号的采样和处理,并在数据存储和访问过程中采用时钟时标方法判断信号采样过程中的数据丢失情况,有效提高了振动信号处理的实时性及可靠性。本设计在真实环境中进行了验证,系统运行稳定可靠,满足各项技术应用要求。
在振動信號採集和處理繫統設計中,信號的處理時間與可靠性決定著繫統應用的可行性。本文設計瞭一種基于FPGA的振動信號採集處理繫統,該繫統通過振動信號採集電路、抗混疊濾波電路、AD採樣電路將電荷信號轉化為數字信號送入FPGA,在FPGA處理設計中利用數據流控製方法併行實現瞭信號的採樣和處理,併在數據存儲和訪問過程中採用時鐘時標方法判斷信號採樣過程中的數據丟失情況,有效提高瞭振動信號處理的實時性及可靠性。本設計在真實環境中進行瞭驗證,繫統運行穩定可靠,滿足各項技術應用要求。
재진동신호채집화처리계통설계중,신호적처리시간여가고성결정착계통응용적가행성。본문설계료일충기우FPGA적진동신호채집처리계통,해계통통과진동신호채집전로、항혼첩려파전로、AD채양전로장전하신호전화위수자신호송입FPGA,재FPGA처리설계중이용수거류공제방법병행실현료신호적채양화처리,병재수거존저화방문과정중채용시종시표방법판단신호채양과정중적수거주실정황,유효제고료진동신호처리적실시성급가고성。본설계재진실배경중진행료험증,계통운행은정가고,만족각항기술응용요구。
In the design of vibration signal acquisition and processing system, the processing time of the signal determines the system sampling frequency, the parallel implementation of the signal processing and signal acquisition process can fulfill the real-time requirement and effectively improve the efficiency of the system. This paper describes the design of a vibration signal acquisition and processing system based on FPGA, the system transfers charge signal into digital quantity into FPGA by vibration signal acquisition circuit, anti-aliasing filter circuit, AD sampling circuit. In the FPGA circuit, we utilize data flow control method for implementing signal sampling and signal processing in parallel, in order to verify the effectiveness of the sampling data in data storage and access, clock time mark method is used to judge the situation of data missing.