CAJ | 학술논문

为充分挖掘多核 DSP 能力，结合 TI 的 TMS320C6678 DSP 的存储器架构，分析了各个关键节点的理论数据传输带宽，展开了对多核 DSP 主设备（ CPU 内核、EDMA 控制器）并行访问存储器（共享 SL2、外部 DDR3）的性能研究，并采用数据拷贝测试实验进行验证，最后讨论了影响带宽的因素，对多核软件设计具有一定的指导意义。
위충분알굴다핵 DSP 능력，결합 TI 적 TMS320C6678 DSP 적존저기가구，분석료각개관건절점적이론수거전수대관，전개료대다핵 DSP 주설비（ CPU 내핵、EDMA 공제기）병행방문존저기（공향 SL2、외부 DDR3）적성능연구，병채용수거고패측시실험진행험증，최후토론료영향대관적인소，대다핵연건설계구유일정적지도의의。
To fully exploit the capabilities of multicore DSP, the paper analyzes the theoretical bandwidth of several key nodes, and studies the parallel performance of multiple masters(CPU cores and EDMA controllers) accessing memory(shared SL2 and external DDR3) with a knowledge of TI TMS320C6678 DSP memory architecture. It is verified by tests of data copying, and finally some factors affecting memory access performance are discussed. Some reference value is provided for designing multicore software system.