电子学报
電子學報
전자학보
ACTA ELECTRONICA SINICA
2014年
6期
1238-1243
,共6页
曾纯%吴宁%张肖强%周芳%叶云飞
曾純%吳寧%張肖彊%週芳%葉雲飛
증순%오저%장초강%주방%협운비
AES%S-盒%多因子CSE算法
AES%S-盒%多因子CSE算法
AES%S-합%다인자CSE산법
advanced encryption standard (AES)%S-box%multiple-term common subexpression elimination (CSE) algo-rithm
针对高级加密标准(AES )S-盒优化,提出了一种新的多因子公共项消除(CSE )优化算法.多因子CSE算法通过对组合逻辑表达式中所含因子最多的公共项优先消除,以简化逻辑表达式,从而有效地减少S-盒电路结构中的GF (2^4)域乘法逆电路和映射矩阵电路的面积和时延.结果表明,多因子CSE算法具有计算速度快,优化效率高的特点.优化后的S-盒组合逻辑电路采用0.18μm CMOS工艺,设计出的S-盒面积-延时积比目前最小面积和最短延时的S-盒组合逻辑电路分别减少了10.32%和19.64%.
針對高級加密標準(AES )S-盒優化,提齣瞭一種新的多因子公共項消除(CSE )優化算法.多因子CSE算法通過對組閤邏輯錶達式中所含因子最多的公共項優先消除,以簡化邏輯錶達式,從而有效地減少S-盒電路結構中的GF (2^4)域乘法逆電路和映射矩陣電路的麵積和時延.結果錶明,多因子CSE算法具有計算速度快,優化效率高的特點.優化後的S-盒組閤邏輯電路採用0.18μm CMOS工藝,設計齣的S-盒麵積-延時積比目前最小麵積和最短延時的S-盒組閤邏輯電路分彆減少瞭10.32%和19.64%.
침대고급가밀표준(AES )S-합우화,제출료일충신적다인자공공항소제(CSE )우화산법.다인자CSE산법통과대조합라집표체식중소함인자최다적공공항우선소제,이간화라집표체식,종이유효지감소S-합전로결구중적GF (2^4)역승법역전로화영사구진전로적면적화시연.결과표명,다인자CSE산법구유계산속도쾌,우화효솔고적특점.우화후적S-합조합라집전로채용0.18μm CMOS공예,설계출적S-합면적-연시적비목전최소면적화최단연시적S-합조합라집전로분별감소료10.32%화19.64%.
Aiming at the optimization of advanced encryption standard (AES) S-box ,a novel multiple-term common subex-pression elimination (CSE ) algorithm was proposed .In order to simplify the combinational logic expressions ,the common subex-pressions containing the most factors took priority to be eliminated in the proposed approach ,thus effectively reduced the area and latency of the GF (2^4 ) multiplicative inverse circuit and the isomorphic mapping circuit in S-box .The results show that the multi-ple-term CSE algorithm achieves high computation and optimization efficiency .The optimized S-box is implemented in 0 .18μm CMOS technology .Compared with the smallest S-box and the shortest delay S-box in the existing work ,the optimized S-box saves about 10 .32% and 19 .64% of the area-delay product separately .