电气电子教学学报
電氣電子教學學報
전기전자교학학보
JOURNAL OF ELECTRICAL & ELECTRONIC ENGINEERING EDUCATION
2014年
3期
83-86
,共4页
FPGA%时序%实验设计
FPGA%時序%實驗設計
FPGA%시서%실험설계
FPGA%timing%experimental design
本文针对 FPGA 教学和程序设计中较难理解的时序问题，阐述了 PLD 电路设计中时序的相关概念并设计了相应的教学实验。本文在调研 PLD 教学现状的基础上，归类整理了与 PLD 设计中与时序相关的基本概念，并依托一个“4比特计数器时序分析”的基础实验设计，加深学生对这些概念的认识和理解。
本文針對 FPGA 教學和程序設計中較難理解的時序問題，闡述瞭 PLD 電路設計中時序的相關概唸併設計瞭相應的教學實驗。本文在調研 PLD 教學現狀的基礎上，歸類整理瞭與 PLD 設計中與時序相關的基本概唸，併依託一箇“4比特計數器時序分析”的基礎實驗設計，加深學生對這些概唸的認識和理解。
본문침대 FPGA 교학화정서설계중교난리해적시서문제，천술료 PLD 전로설계중시서적상관개념병설계료상응적교학실험。본문재조연 PLD 교학현상적기출상，귀류정리료여 PLD 설계중여시서상관적기본개념，병의탁일개“4비특계수기시서분석”적기출실험설계，가심학생대저사개념적인식화리해。
In order to help the students better understanding the concepts of FPGA timing,the relevant concepts of timing in PLD circuit is discussed together with the appropriate experiments. The investigation of the available sta-tus of PLD teaching is introduced first. Then this paper made a classification of several basic concepts on Timing re-lated to the PLD design. At last,a fundamental experiment to explore the FPGA timing by a 4-bit counter design experiment is presented,which can deepen students′ understanding of these concepts.
