CAJ | 학술논문

采用部分更新最小均方(LMS)算法和重叠保留的块信号频域处理结构，针对现场可编程门阵列(FPGA)的硬件实现平台，提出了时频混合部分更新块LMS和周期性块部分更新LMS均衡算法结构。2种新结构均能有效降低均衡算法的实现复杂度。步长收敛条件分析和数值仿真结果表明，新结构能够在适当调整更新步长的情况下，有效跟踪缓变信道的变化，实现与完整块LMS算法相当的性能，能够有效解决高速数据传输中的均衡复杂度过高的问题。
채용부분경신최소균방(LMS)산법화중첩보류적괴신호빈역처리결구，침대현장가편정문진렬(FPGA)적경건실현평태，제출료시빈혼합부분경신괴LMS화주기성괴부분경신LMS균형산법결구。2충신결구균능유효강저균형산법적실현복잡도。보장수렴조건분석화수치방진결과표명，신결구능구재괄당조정경신보장적정황하，유효근종완변신도적변화，실현여완정괴LMS산법상당적성능，능구유효해결고속수거전수중적균형복잡도과고적문제。
By-adopting-partial-update-Least-Mean-Square(LMS)-algorithm-and-block-processing-structure-featured-with-over-lapping-and-saving-frequency-domain,-a-hybrid-time-frequency-partial-update-block-LMS-equalization-structure-and-periodic-block-partial-update-LMS-equalization-structure-are-proposed-for-the-Field-Programmable-Gate-Array(FPGA)-platform.-Both-the-two-new-structures-can-effectively-reduce-the-equalization-computational-complexity.-Analysis-of-convergence-condition-of-step-size-and-numerical-simulation-results-show-that-the-new-structures-can-effectively-track-the-slowly-time-varying-channels-with-proper-adjustment-of-the-step-size-and-achieve-comparable-performance-as-the-complete-block-LMS-algorithm;-and-the-problem-of-high-computational-complexity-equalizer-in-high-speed-communication-could-be-effectively-solved.