CAJ | 학술논문

为满足激光雷达系统多通道、精确处理大量时间数据的需求,利用抽头延时线技术,在Virtex6 FPGA上采用Veril-og语言实现了时间数字转换电路( Time-to-Digital Convertor,TDC)。文中在领域分析的基础上明确了时间数字转换电路的主要原理,对电路的各模块进行详细设计,并通过GPX测试芯片与在FPGA内部实现的TDC电路进行实时对比测试,修正系统固定误差。实验表明,该课题设计的多通道TDC电路各通道间的测量误差在1 LSB左右,每个通道测量分辨率可达58 ps。采用GPX芯片进行校准测试的方案排除了信号源误差,优于传统检校方案。
위만족격광뢰체계통다통도、정학처리대량시간수거적수구,이용추두연시선기술,재Virtex6 FPGA상채용Veril-og어언실현료시간수자전환전로( Time-to-Digital Convertor,TDC)。문중재영역분석적기출상명학료시간수자전환전로적주요원리,대전로적각모괴진행상세설계,병통과GPX측시심편여재FPGA내부실현적TDC전로진행실시대비측시,수정계통고정오차。실험표명,해과제설계적다통도TDC전로각통도간적측량오차재1 LSB좌우,매개통도측량분변솔가체58 ps。채용GPX심편진행교준측시적방안배제료신호원오차,우우전통검교방안。
In order to meet the requirement of LiDAR ( Light Detection And Ranging) system in measuring precise time with multiple channels,a Time-to-Digital Convertor ( TDC) using tapped delay line technology is implemented with Verilog HDL upon Virtex6 FP-GA. The main principle of TDC is clarified based on domain analysis,and then each module of the circuit is designed in detail. Further-more,the fixed error of the designed TDC is calibrated with the more precise GPX timing chip. Experimental data shows that not only an accuracy of 1 LSB is achieved in all 48 channels,but also the time resolution of a single channel is improved to 58 ps. The calibration scheme adopting the GPX chip has eliminated the error of the signal source, which is consequently more reliable than the traditional scheme.