电子与封装
電子與封裝
전자여봉장
EIECTRONICS AND PACKAGING
2014年
8期
18-24,41
,共8页
同步动态随机存储器%DSIO%J750EX
同步動態隨機存儲器%DSIO%J750EX
동보동태수궤존저기%DSIO%J750EX
SDRAM%DSIO%J750EX
SDRAM(Synchronous Dynamic Random Access Memory,同步动态随机存储器)以其卓越的性能、低廉的价格得到了广泛的应用,但由于此类器件具有容量较大(通常为百兆级及以上)、对其实施控制较复杂等特点,使得SDRAM的测试也存在较高难度,因此,探索SDRAM的测试技术,并创建该类器件的测试平台也具有十分重要的意义。首先介绍了SDRAM的基本工作原理,其次详细阐述了基于J750EX测试系统的测试技术研究,提出了采用J750EX系统的DSIO资源实现SDRAM地址累加生成的方法,大大减少了测试矢量长度,可以有效节省测试开发时间,降低测试成本。另外,针对SDRAM的关键时序参数,如tRCD(行选通周期)、CL(读取潜伏期)、tWR(写回时间)等,使用测试系统为器件施加适当的控制激励,完成SDRAM复杂的时序配合,从而达到器件性能的测试要求。
SDRAM(Synchronous Dynamic Random Access Memory,同步動態隨機存儲器)以其卓越的性能、低廉的價格得到瞭廣汎的應用,但由于此類器件具有容量較大(通常為百兆級及以上)、對其實施控製較複雜等特點,使得SDRAM的測試也存在較高難度,因此,探索SDRAM的測試技術,併創建該類器件的測試平檯也具有十分重要的意義。首先介紹瞭SDRAM的基本工作原理,其次詳細闡述瞭基于J750EX測試繫統的測試技術研究,提齣瞭採用J750EX繫統的DSIO資源實現SDRAM地阯纍加生成的方法,大大減少瞭測試矢量長度,可以有效節省測試開髮時間,降低測試成本。另外,針對SDRAM的關鍵時序參數,如tRCD(行選通週期)、CL(讀取潛伏期)、tWR(寫迴時間)等,使用測試繫統為器件施加適噹的控製激勵,完成SDRAM複雜的時序配閤,從而達到器件性能的測試要求。
SDRAM(Synchronous Dynamic Random Access Memory,동보동태수궤존저기)이기탁월적성능、저렴적개격득도료엄범적응용,단유우차류기건구유용량교대(통상위백조급급이상)、대기실시공제교복잡등특점,사득SDRAM적측시야존재교고난도,인차,탐색SDRAM적측시기술,병창건해류기건적측시평태야구유십분중요적의의。수선개소료SDRAM적기본공작원리,기차상세천술료기우J750EX측시계통적측시기술연구,제출료채용J750EX계통적DSIO자원실현SDRAM지지루가생성적방법,대대감소료측시시량장도,가이유효절성측시개발시간,강저측시성본。령외,침대SDRAM적관건시서삼수,여tRCD(행선통주기)、CL(독취잠복기)、tWR(사회시간)등,사용측시계통위기건시가괄당적공제격려,완성SDRAM복잡적시서배합,종이체도기건성능적측시요구。
The SDRAM(Synchronous Dynamic Random Access Memory) has been widely used for its excellent performance, low price, but due to the fact that the device has a larger capacity (usually a 100 Mb level and above) and the complexity of the implementation for controling, it makes the testing of SDRAM become more difficult, therefore, to explore the SDRAM test technology and create test platform for this kind of the device also has a very important significance. The paper introduces the basic working principle of SDRAM, followed by a detailed describe to the study of the test technology based on J750EX testing system, proposed a method using DSIO resources to achieve the accumulated generating operation of the address for SDRAM. It’s greatly reducing the length of test vectors. It can effectively economize the test time, and reduce the cost of testing. In addition, the key timing parameters of SDRAM, such as tRCD (row strobe cycle), CL (read latency), tWR (write back time), can be tested using the test system to send the appropriate control excitations for the device to complete the complicated time cooperate of SDRAM, so that the test requirements of the performance for the device can be achieved.