CAJ | 학술논문

基于0沣．5μm CMOS工艺设计并制备了一种应用于红外焦平面读出电路的多层堆叠（ stack）电容结构，测试结果表明，相比单一形式电容，stack电容的单位面积值增大两倍以上，因而能够有效地提升红外焦平面读出电路的电荷存储能力。此外，本文还为设计的多层stack电容建立了一套描述其电学特性的 SPICE模型，模型均方根误差在2％以内，因此可以准确描述stack电容的电学特性，满足了红外焦平面读出电路的仿真设计要求。
기우0풍．5μm CMOS공예설계병제비료일충응용우홍외초평면독출전로적다층퇴첩（ stack）전용결구，측시결과표명，상비단일형식전용，stack전용적단위면적치증대량배이상，인이능구유효지제승홍외초평면독출전로적전하존저능력。차외，본문환위설계적다층stack전용건립료일투묘술기전학특성적 SPICE모형，모형균방근오차재2％이내，인차가이준학묘술stack전용적전학특성，만족료홍외초평면독출전로적방진설계요구。
A multi-layer stack capacitance is designed and fabricated which is applied to infrared fo -cal plane array readout circuit ( IRFPA ROIC) .The test results indicate that the unit-area stack capaci-tance increases more than two times compared with the single -form capacitance, which enhances the ca-pacity of charge storage for IRFPA ROIC .Moreover , a SPICE model for the stack capacitance is built to describe its electrical characteristic , and the root mean square error ( RMSE) of the SPICE model is less than 2%.Therefore , it can describe the electrical characteristic of the stack capacitance accurately and meet the requirements of the simulation design of IRFPA ROIC .