系统工程与电子技术
繫統工程與電子技術
계통공정여전자기술
SYSTEMS ENGINEERING AND ELECTRONICS
2014年
11期
2320-2325
,共6页
频率值总线反转编码%低功耗%总线编码%时分复用技术
頻率值總線反轉編碼%低功耗%總線編碼%時分複用技術
빈솔치총선반전편마%저공모%총선편마%시분복용기술
frequent value and bus invert (FV-BI)coding%low power%bus coding%time division multiple-xing technique
对频率值(frequent value,FV)编码技术进行了改进,并结合总线反转(bus invert,BI)编码技术的优点提出了 FV-BI 自适应总线编码,利用时分复用技术解决了多套数据总线混合编码问题和需要两根额外数据线问题。基于基准测试程序、图片及音视频和随机数的测试,结果表明提出的 FV-BI 自适应总线编码技术能降低22%~53%的开关活动,相比单独 FV 编码和 BI 编码技术开关活动降低2~4倍。利用 Matlab 软件和 Prime-Power 软件,在0.18μm 工艺下针对不同互连线长度进行行为级和 sign-off 级功耗估计,结果表明在接近10 mm互连线长度下,FV-BI 自适应编码技术能有效降低芯片功耗。最后完成了 FV、BI 和 FV-BI 自适应编码技术在现场可编程门阵列(field programmable gate array,FPGA)的实现,利用 Xpower 软件分析其功耗,并进行 FPGA 板级测试,结果也证明了 FV-BI 编码技术降低功耗的有效性。
對頻率值(frequent value,FV)編碼技術進行瞭改進,併結閤總線反轉(bus invert,BI)編碼技術的優點提齣瞭 FV-BI 自適應總線編碼,利用時分複用技術解決瞭多套數據總線混閤編碼問題和需要兩根額外數據線問題。基于基準測試程序、圖片及音視頻和隨機數的測試,結果錶明提齣的 FV-BI 自適應總線編碼技術能降低22%~53%的開關活動,相比單獨 FV 編碼和 BI 編碼技術開關活動降低2~4倍。利用 Matlab 軟件和 Prime-Power 軟件,在0.18μm 工藝下針對不同互連線長度進行行為級和 sign-off 級功耗估計,結果錶明在接近10 mm互連線長度下,FV-BI 自適應編碼技術能有效降低芯片功耗。最後完成瞭 FV、BI 和 FV-BI 自適應編碼技術在現場可編程門陣列(field programmable gate array,FPGA)的實現,利用 Xpower 軟件分析其功耗,併進行 FPGA 闆級測試,結果也證明瞭 FV-BI 編碼技術降低功耗的有效性。
대빈솔치(frequent value,FV)편마기술진행료개진,병결합총선반전(bus invert,BI)편마기술적우점제출료 FV-BI 자괄응총선편마,이용시분복용기술해결료다투수거총선혼합편마문제화수요량근액외수거선문제。기우기준측시정서、도편급음시빈화수궤수적측시,결과표명제출적 FV-BI 자괄응총선편마기술능강저22%~53%적개관활동,상비단독 FV 편마화 BI 편마기술개관활동강저2~4배。이용 Matlab 연건화 Prime-Power 연건,재0.18μm 공예하침대불동호련선장도진행행위급화 sign-off 급공모고계,결과표명재접근10 mm호련선장도하,FV-BI 자괄응편마기술능유효강저심편공모。최후완성료 FV、BI 화 FV-BI 자괄응편마기술재현장가편정문진렬(field programmable gate array,FPGA)적실현,이용 Xpower 연건분석기공모,병진행 FPGA 판급측시,결과야증명료 FV-BI 편마기술강저공모적유효성。
By combining the advantage of the improved frequent value (FV)and bus invert (BI)coding techniques,the FV-BI adaptive bus coding is proposed,which mainly uses time division multiplexing technique to solve multiple sets of data bus coding and two additional data line problems.Experiment results show that FV-BI coding yields a 22% 53% reduction in data bus switching activity for benchmark programs in addition picture, audio/video and random testing data.Moreover the reduction in switching activity by FV-BI is 2 4 times the re-duction achieved by BI and FV alone.Meanwhile the power estimation of system level and sign-off level by Mat-lab and PrimePower program in 0.18 μm process technology is given.The results in 10 mm interconnect length show that the FV-BI adaptive coding technique can effectively reduce the power of chip.Finally,the FV,BI and FV-BI coding techniques are implemented in field programmable gate array (FPGA)and evaluate the power based on Xpower program and board testing.The results also show that FV-BI coding scheme is effectively re-duced the power of interconnect system.