计算机工程与设计
計算機工程與設計
계산궤공정여설계
COMPUTER ENGINEERING AND DESIGN
2014年
10期
3422-3427
,共6页
A/D转换器%A/D控制器%多通道转换控制器%结果寄存器%微处理器
A/D轉換器%A/D控製器%多通道轉換控製器%結果寄存器%微處理器
A/D전환기%A/D공제기%다통도전환공제기%결과기존기%미처리기
A/D converter%A/D controller%multi-channel switch controller%result register%microprocessor
为减轻微处理器频繁控制A/D转换器转换时序与读取A/D转换结果的负担，提出串行 A/D转换器 M AX192的FPGA控制方法。根据M AX192多通道转换时序的特点，设计基于FPGA的多通道转换控制器和 A/D转换结果寄存器阵列。由微控制器指定采样周期、采样点数、采样通道顺序和最大转换通道数等参数来控制 FPGA ，对M AX192进行转换，且每个采样通道配置1个结果寄存器组，其数量由最大采样通道数决定。仿真结果表明，基于FPGA的M AX192控制器对多通道信号连续转换时，每个通道的平均转换时间与单通道单独转换相比减少了37.5％；结果寄存器可及时存储每次转换结果，便于微处理器及时读取A/D转换结果进行后续快速数字信号处理运算，提高了数据采集系统的实时性，具有工程应用价值。
為減輕微處理器頻繁控製A/D轉換器轉換時序與讀取A/D轉換結果的負擔，提齣串行 A/D轉換器 M AX192的FPGA控製方法。根據M AX192多通道轉換時序的特點，設計基于FPGA的多通道轉換控製器和 A/D轉換結果寄存器陣列。由微控製器指定採樣週期、採樣點數、採樣通道順序和最大轉換通道數等參數來控製 FPGA ，對M AX192進行轉換，且每箇採樣通道配置1箇結果寄存器組，其數量由最大採樣通道數決定。倣真結果錶明，基于FPGA的M AX192控製器對多通道信號連續轉換時，每箇通道的平均轉換時間與單通道單獨轉換相比減少瞭37.5％；結果寄存器可及時存儲每次轉換結果，便于微處理器及時讀取A/D轉換結果進行後續快速數字信號處理運算，提高瞭數據採集繫統的實時性，具有工程應用價值。
위감경미처리기빈번공제A/D전환기전환시서여독취A/D전환결과적부담，제출천행 A/D전환기 M AX192적FPGA공제방법。근거M AX192다통도전환시서적특점，설계기우FPGA적다통도전환공제기화 A/D전환결과기존기진렬。유미공제기지정채양주기、채양점수、채양통도순서화최대전환통도수등삼수래공제 FPGA ，대M AX192진행전환，차매개채양통도배치1개결과기존기조，기수량유최대채양통도수결정。방진결과표명，기우FPGA적M AX192공제기대다통도신호련속전환시，매개통도적평균전환시간여단통도단독전환상비감소료37.5％；결과기존기가급시존저매차전환결과，편우미처리기급시독취A/D전환결과진행후속쾌속수자신호처리운산，제고료수거채집계통적실시성，구유공정응용개치。
To reduce the burden of the microprocessor on frequently controlling the A/D converter’s conversion timing and rea-ding A/D conversion results ,the MAX192 controller design method based on the FPGA was proposed .According to the charac-teristics of the MAX192 multi-channel conversion timing ,the multi-channel switch controller and the array of A/D conversion results registers were designed .The sampling period ,sampling points ,the sampling channel order and the maximum conversion parameters were designated by the microcontroller .A result set of registers was configured to each sampling channel ,and the number was decided by the maximum sampling channel number .The simulation result shows that the average conversion time of each channel is decreased by 37.5% compared with that of the single channel conversion when multi-channel sequential conver-sions are controlled by the MAX192 controller based on the FPGA sample .Results registers can store the converted results in time to facilitate the microprocessor to timely read the A/D conversion results for subsequent fast digital signal processing opera-tions .T he timeliness of the data acquisition system is improved .It has engineering application value .
