计算机工程
計算機工程
계산궤공정
COMPUTER ENGINEERING
2014年
10期
114-117
,共4页
朱坤顺%杨红官%樊晓华%乔树山
硃坤順%楊紅官%樊曉華%喬樹山
주곤순%양홍관%번효화%교수산
维特比译码器%低功耗%加-比-选%路径度量存储%路径相消%幸存路径
維特比譯碼器%低功耗%加-比-選%路徑度量存儲%路徑相消%倖存路徑
유특비역마기%저공모%가-비-선%로경도량존저%로경상소%행존로경
Viterbi decoder%low power%Add-compare-select ( ACS )%path metric memory%path mutual eliminating%survivor path
针对无线通信中低功耗维特比译码器设计结构复杂的问题,提出一种四级流水串并结合的(2,1,9)低功耗维特比译码器。该译码器采用改进的加-比-选( ACS)单元,以降低硬件复杂度,在提高时钟运行速率的基础上减少运行功耗。幸存路径存储单元采用改进的路径相消方法,减少译码器的输出延迟,提高译码效率。性能分析结果表明,基于TSMC 0．18μm CMOS逻辑工艺,在1．62 V,125℃操作环境下,该译码器数据最大速度为50 MHz,自动布局布线后的译码器芯片面积约为0．212 mm2,功耗约为23．9 mW。
針對無線通信中低功耗維特比譯碼器設計結構複雜的問題,提齣一種四級流水串併結閤的(2,1,9)低功耗維特比譯碼器。該譯碼器採用改進的加-比-選( ACS)單元,以降低硬件複雜度,在提高時鐘運行速率的基礎上減少運行功耗。倖存路徑存儲單元採用改進的路徑相消方法,減少譯碼器的輸齣延遲,提高譯碼效率。性能分析結果錶明,基于TSMC 0．18μm CMOS邏輯工藝,在1．62 V,125℃操作環境下,該譯碼器數據最大速度為50 MHz,自動佈跼佈線後的譯碼器芯片麵積約為0．212 mm2,功耗約為23．9 mW。
침대무선통신중저공모유특비역마기설계결구복잡적문제,제출일충사급류수천병결합적(2,1,9)저공모유특비역마기。해역마기채용개진적가-비-선( ACS)단원,이강저경건복잡도,재제고시종운행속솔적기출상감소운행공모。행존로경존저단원채용개진적로경상소방법,감소역마기적수출연지,제고역마효솔。성능분석결과표명,기우TSMC 0．18μm CMOS라집공예,재1．62 V,125℃조작배경하,해역마기수거최대속도위50 MHz,자동포국포선후적역마기심편면적약위0．212 mm2,공모약위23．9 mW。
Toward the complicated structure of low power implementation of the Viterbi decoder in wireless communication,a low power (2,1,9) Viterbi decoder with the structure of series and parallel combination in four-level pipeline is proposed in the paper. To increase working rate, with the consideration of the implementation hardware complexity,a modified Add-compare-select( ACS) unit is used to satisfy its low power decoding requirment. In order to increase the efficiency of decoding and decrease the latency of decoder,a method of path mutual eliminating is employed in the design. Implemented by TSMC 0. 18 μm standard CMOS technology under 1. 62 V and 125 ℃,and analysed with placement and route,the chip’ s highest speed is about 50 MHz,the area is 0. 212 mm2 ,and the power comsumption is 23. 9 mW.
